Electronic memories
A server memory module is 72 bits wide to store 64: the remaining eight correct any bit that a cosmic ray flips.
01What distinguishes one memory from another
A memory stores bits in cells, and each technology stores the bit in a different physical way: the state of a flip-flop, the charge of a capacitor, the charge trapped on an insulated gate, or the polarization of a material. All of its properties follow from that physical form: whether it loses the data when power is removed, how long it takes to read and write, how many times it can be rewritten, and how much area each bit takes. The technician program page presents the types; here we see why they are the way they are.
| Memory | Cell | Volatile? | Rewrites | Use |
|---|---|---|---|---|
| SRAM | 6 transistors (flip-flop) | Yes | Unlimited | Registers, cache, microcontroller RAM |
| DRAM | 1 transistor and 1 capacitor | Yes, and it must also be refreshed | Unlimited | Main memory of computers |
| NOR flash | Floating-gate transistor | No | About 100,000 | Microcontroller program; executed in place |
| NAND flash | Floating gate or charge trap, in series | No | From 1000 to 100,000 depending on bits per cell | Solid-state drives, SD cards |
| EEPROM | Floating gate with byte-wise erase | No | Around one million | Configuration and calibration |
| FRAM | Ferroelectric capacitor | No | On the order of 1014 | Frequent data logging at low power |
02Internal organization
The cells form a matrix of rows and columns. A row decoder activates an entire row, the sense amplifiers detect the small voltage differences on its columns, and a column multiplexer chooses which ones come out. A memory of \( 2^A \) words of \( w \) bits needs \( A \) address lines and \( w \) data lines: a 128 K × 8 one has 17 address lines and 8 data lines.
In a system with several memories and peripherals, address decoding divides up the space: the high bits of the address choose which chip is enabled, through its select signal, and the low bits choose the word within the chip. The result is the system’s memory map.
03SRAM and DRAM
The SRAM cell is a flip-flop of two cross-coupled inverters plus two access transistors: it holds the data as long as power is applied, is read without destroying it, and is fast, but takes six transistors per bit.
The DRAM cell stores the bit as the charge on a capacitor of a few femtofarads, behind a transistor. It is much denser, but the charge leaks away and each cell must be refreshed, typically every 64 ms, and reading discharges the capacitor, so every read is followed by a rewrite. DRAMs multiplex the address: first the row, then the column. DDR memories transfer on both clock edges: a DDR4-3200 module makes 3200 million transfers of 64 bits per second, 25.6 GB/s.
04Nonvolatile memories
In a flash cell, the bit is the charge trapped on a gate surrounded by oxide. That charge shifts the threshold of the transistor, and the read detects whether it conducts or not. To write and erase, charge is driven through the oxide with high fields, and each pass wears it down a little: that is why the number of rewrites is limited.
| NOR | NAND | |
|---|---|---|
| Access | Random by word, like a RAM | By pages of kilobytes |
| Erase | By sectors | By blocks of hundreds of pages |
| Density and cost per bit | Lower density, higher cost | Maximum density, minimum cost |
| Management | Almost none | Error correction, bad blocks and wear leveling |
Storing more than one bit per cell, with several charge levels, multiplies the capacity but narrows the margins between levels: a one-bit cell (SLC) withstands on the order of 100,000 erase cycles; a three-bit one (TLC), a few thousand.
05Errors and error-correcting codes
No memory is perfect. An alpha particle from the package or a neutron from cosmic rays can flip a bit in a DRAM or an SRAM (a soft error), and in a flash the bits degrade with use. Systems that cannot fail store, along with each word, parity bits computed with a Hamming code. To correct one error in \( m \) data bits, \( r \) parity bits are needed such that:
In the Hamming code, the parity bits go in the positions that are powers of two, and each one covers the positions whose binary number has that bit set to 1. On reading, the parities are recomputed: the binary number formed by those that fail, the syndrome, is directly the position of the erroneous bit.
Four data bits are encoded into eight: three Hamming parities in positions 1, 2 and 4, and a global parity in position 0. You choose the data, then click the stored bits to alter them, as a particle would, and the decoder responds.
06Where it appears in electronics
| System | Memories it uses |
|---|---|
| Microcontroller | NOR flash for the program, SRAM for the data, sometimes EEPROM emulated in flash |
| Server | DRAM with 72-bit SECDED ECC |
| Solid-state drive | NAND with a controller that corrects errors and spreads the wear |
| Satellite | Radiation-hardened memories, with ECC and periodic rereading (scrubbing) |
| Energy meter | FRAM or EEPROM for the registers that change often |
07In the lab
Design the address decoding of a system with a 32 K × 8 EPROM, an 8 K × 8 SRAM and a peripheral with 16 registers on a 16-bit address bus. Draw the map.
With a microcontroller, write a page to a serial EEPROM, measure the write time and verify the readback.
Program the SECDED encoding and decoding of a byte and inject errors to test the correction.
08Common mistakes
- Writing to flash too often. A log written every second uses up 100,000 cycles in a little over a day.
- Forgetting that flash is erased in blocks. Changing one byte requires erasing and rewriting the entire block.
- Confusing capacity in bits and in bytes. An 8 Mbit chip has 1 MB.
- Believing that simple parity corrects. It only detects an odd number of errors.
09Self-assessment
How many address lines does a 512 K × 16 memory have?
19, because \( 2^{19} = 524\,288 \).
How many parity bits does a Hamming code that corrects one error in 16 bits need?
Five: \( 2^5 = 32 \ge 16 + 5 + 1 \). With SECDED, six.
In a Hamming (7,4) code, parities 1 and 4 fail and parity 2 does not. Which bit is wrong?
The one in position 5 (101 in binary).
Why does a DRAM need refresh and an SRAM does not?
Because it stores the bit as charge on a capacitor that discharges through leakage; the SRAM stores it in a flip-flop that sustains itself as long as power is applied.
10Further reading
- Bruce Jacob, Spencer W. Ng and David T. Wang. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann, 2008. The reference on the organization, timing and design of memory systems.
- Betty Prince. Semiconductor Memories: A Handbook of Design, Manufacture and Application. 2nd ed., Wiley, 1991. The cells and circuits of each type of memory, from inside the chip.
- Shu Lin and Daniel J. Costello. Error Control Coding. 2nd ed., Pearson, 2004. Hamming codes and their successors, with the complete theory.