Analog-to-digital and digital-to-analog converters
A 14-bit converter sampling a 49 MHz signal with a clock of 1 ps jitter performs the same as an 11-bit one: the clock, not the converter, sets the limit.
01The boundary between analog and digital
Every digital system that measures or acts on the world has a converter at each edge: an analog-to-digital converter (ADC) that turns a voltage into a number, and a digital-to-analog converter (DAC) that does the opposite. Between the two there can be the most sophisticated processing, but the quality of the system never exceeds that of its converters. The technician program page presents the basic circuits; here the subject is how they are specified, what limits them, and how to choose an architecture.
Conversion has two independent steps. Sampling discretizes time and requires, by the Shannon theorem, a sampling frequency greater than twice the bandwidth of the signal, with an anti-aliasing filter in front. Quantization discretizes the amplitude, and it is the subject proper to this page.
02Quantization and signal-to-noise ratio
An \( N \)-bit converter with input range \( FS \) divides that range into \( 2^N \) steps of width \( \Delta = FS / 2^N \), the LSB. Each sample is rounded to the nearest step, with an error between \( -\Delta/2 \) and \( +\Delta/2 \). For a signal that sweeps across many steps, that error behaves like uniform noise with an RMS value of \( \Delta/\sqrt{12} \). Compared with a sine wave that fills the whole range:
The quantization noise is spread between 0 and \( f_s/2 \). In a spectrum computed with an \( M \)-point FFT, each bin receives only a part of it, and the floor appears \( 10 \log(M/2) \) dB below the total noise level: with 4096 points, 33 dB. That is why the spectrum of a 12-bit converter shows its floor near −107 dBFS even though its signal-to-noise ratio is 74 dB.
03Static and dynamic specifications
| Parameter | What it measures |
|---|---|
| Offset and gain error | The shift of zero and the slope of the characteristic; they are calibrated out |
| DNL (differential nonlinearity) | How far each step deviates from 1 LSB; with a DNL of −1 LSB a code is lost |
| INL (integral nonlinearity) | The maximum distance between the real characteristic and the ideal straight line |
| SINAD | Signal versus noise plus distortion: the measure from which the ENOB comes |
| SFDR | Distance between the signal and the highest spur; decisive in radio receivers |
There is a limit that does not depend on the converter: the uncertainty in the sampling instant. A clock with RMS jitter \( t_j \) takes each sample a little early or late, and on a fast-changing signal that timing error becomes an amplitude error:
A sine wave close to full scale, sampled at 100 MS/s and quantized with \( N \) bits, with a clock that can have jitter. 4096 samples are taken, the FFT is computed and the signal-to-noise ratio is measured. The input frequency completes a whole number of cycles in the window, so that the signal falls into a single bin.
04ADC architectures
| Architecture | How it converts | Typical resolution and speed |
|---|---|---|
| Flash | \( 2^N - 1 \) comparators in parallel, one per threshold | 6 to 8 bits, gigasamples per second; 255 comparators for 8 bits |
| Successive approximation (SAR) | Binary search with a DAC and a comparator: one bit per cycle | 10 to 18 bits, up to tens of MS/s; the one in almost all microcontrollers |
| Pipeline | Cascaded stages that each resolve a few bits and pass the amplified remainder on | 12 to 16 bits, hundreds of MS/s; software-defined radio |
| Sigma-delta | A heavily oversampled 1-bit modulator and a digital filter that averages | 16 to 24 bits, up to hundreds of kS/s; audio and measurement |
| Dual slope | Integrates the input and counts the discharge time | Slow and very linear; multimeters |
The sigma-delta trades speed for resolution. Plain oversampling gains 3 dB each time the sampling frequency doubles, because the quantization noise is spread over a wider band and the filter lets only a part of it through. The modulator also shapes the noise: it pushes it toward high frequencies, outside the useful band. A first-order modulator gains 9 dB per doubling; a second-order one, 15 dB.
05Digital-to-analog converters
A DAC sums binary weights. The R-2R network obtains them with only two resistance values; the resistor string with \( 2^N \) taps is monotonic by construction; current-source switched DACs are the fastest, and sigma-delta DACs dominate audio. At the output, the DAC holds each value for one period: this zero-order hold attenuates the response with a \( \sin(x)/x \) shape, 3.9 dB at half the sampling frequency, and leaves images of the spectrum around the multiples of \( f_s \), which a reconstruction filter removes.
06Where it appears in electronics
| System | Typical converter |
|---|---|
| Microcontroller | 12-bit SAR at 1 MS/s, with an input multiplexer |
| Audio interface | 24-bit sigma-delta at 48 or 96 kS/s |
| Scale or bridge sensor | 24-bit sigma-delta at a few samples per second |
| Digital oscilloscope | Flash or interleaved 8-bit arrays at gigasamples |
| Software-defined radio | 14-bit pipeline at hundreds of MS/s, with a low-jitter clock |
07In the lab
Digitize a sine wave from a low-distortion generator with a microcontroller’s ADC, send 4096 samples to the computer, compute the FFT and obtain the SINAD and the effective bits.
Apply a slow ramp, build the code histogram and compute the DNL of each code. Look for missing codes.
Build an 8-bit R-2R DAC with 1 % resistors and measure its INL. Repeat with 0.1 % resistors and compare.
08Common mistakes
- Confusing resolution with accuracy. A 16-bit ADC with 4 LSB of INL is not accurate to 16 bits.
- Reading the FFT floor as the total noise. You have to add \( 10\log(M/2) \) dB to it.
- Ignoring the clock jitter. At high input frequencies it limits performance more than the bits do.
- Omitting the anti-aliasing filter. Everything above \( f_s/2 \) folds onto the useful band and cannot be separated afterward.
09Self-assessment
What ideal SNR does a 16-bit converter have?
\( 6.02 \cdot 16 + 1.76 = 98.1 \) dB.
An ADC measures 62 dB of SINAD. How many effective bits does it have?
\( (62 - 1.76)/6.02 = 10 \) bits.
What maximum jitter does a system that samples 10 MHz with 80 dB of SNR allow?
\( t_j = 10^{-4}/(2\pi \cdot 10^7) \approx 1.6 \) ps.
How many clock cycles does a 12-bit SAR need to convert?
Twelve, one per bit, plus the acquisition time.
10Further reading
- Walt Kester (ed.). Data Conversion Handbook. Analog Devices and Newnes, 2005. The practical reference: specifications, architectures, tests and applications of ADCs and DACs.
- Marcel J. M. Pelgrom. Analog-to-Digital Conversion. 3rd ed., Springer, 2017. The design treatment, from sampling to sigma-delta converters, with the physical limits of each architecture.
- Behzad Razavi. Principles of Data Conversion System Design. IEEE Press, 1995. Brief and clear on the architectures and their errors.