Programmable systems and memories
Two topics that look different and are really the same: storing bits in one place and reading them back later. A memory stores data; a programmable logic device stores the function the circuit is going to perform.
01The map of memories
| Type | Volatile | Write | Cycles | Where you find it |
|---|---|---|---|---|
| SRAM | Yes | Immediate | Unlimited | Microcontroller variables, processor cache. Fast and expensive: six transistors per bit. |
| DRAM | Yes | Immediate | Unlimited | Main memory of a PC. One transistor and one capacitor per bit: cheap and dense, but it needs constant refreshing. |
| Mask ROM | No | At the factory | — | Burned into the silicon. Only justified in huge production runs. |
| PROM | No | Once | 1 | Internal fuses are “blown.” Historical. |
| EPROM (UVPROM) | No | Electrical | ~100 | The one with the little quartz window: it is erased with ultraviolet light in 20 minutes. Still found in old industrial equipment. |
| EEPROM | No | Byte by byte | ~106 | Configuration and calibration. Slow to write (milliseconds per byte). |
| Flash NOR | No | By blocks | ~105 | Microcontroller program memory and BIOS. It is read byte by byte, which allows executing code directly from it. |
| Flash NAND | No | By pages | 103–105 | USB flash drives, SD cards, SSDs. Much denser and cheaper, but it can only be read by pages. |
| FRAM | No | Immediate | 1014 | Continuous data logging without wear-out. Expensive and low capacity. |
- Does it lose its contents when power is removed? Volatile or non-volatile.
- How many times can it be written? That number —the endurance— decides whether it is suitable for storing a value that changes all the time.
- How fast does it respond? Nanoseconds in SRAM, microseconds when reading Flash, milliseconds when writing an EEPROM.
A NAND Flash cell in a cheap USB flash drive withstands about 3000 cycles of erasing. If a program always wrote to the same location, the drive would die within minutes. What prevents this is wear leveling: the controller spreads the writes over the whole chip and keeps a map of which physical block corresponds to each logical address. It is a complete system, with its own processor, inside every USB flash drive and every SSD.
02How it is organized and how it is selected
A memory is an array of cells with three groups of pins: address, data and control. Capacity is written as “words × bits”: a 62256 is 32 K × 8, that is, 32,768 locations of one byte.
| Signal | Name | What it does |
|---|---|---|
| CS̄ / CĒ | Chip select | Enables the chip. This is what allows several memories on the same bus: only the selected one responds. |
| OĒ | Output enable | Puts the data on the bus. Without it, the outputs stay in high impedance. |
| WĒ | Write enable | Writes what is on the data bus to the address that is present. |
| A0…An | Address | Select the location. |
| D0…D7 | Data | Bidirectional, with three-state outputs. |
- Each 32 K chip needs 15 address lines (A0 to A14), because 215 = 32,768.
- Line A15 does not go to the chips: it is used to choose which one responds. With A15 = 0 the first is enabled (addresses 0000 to 7FFF) and with A15 = 1 the second (8000 to FFFF).
- With four chips, A15 and A16 would be used with a 2-to-4 decoder; with eight, three lines and a 74HC138.
If two chips were enabled at the same time, both would put data on the bus: it is a short circuit between outputs, exactly what the ERC of the schematic warns about.
03Programmable logic devices
A circuit with fifty gates can be built with fifteen 74-series ICs —taking up half a circuit board— or with a single programmable chip that is configured by software. That is the whole idea, and its evolution has three stages.
An array of programmable connections between the inputs and a set of AND-OR gates. They replace around ten 74-series ICs. The GAL22V10 was for years the wild card of any digital design.
Several GAL-type blocks joined by an interconnect matrix. Hundreds of macrocells, non-volatile configuration —it works as soon as it is powered on— and very predictable timing. Ideal for glue logic and decoding.
Thousands or millions of logic blocks with memory, multipliers and even processors inside. It is configured at power-up from an external Flash. This is what makes it possible to create custom hardware: twenty counters running in parallel, with none waiting for another.
You do not draw gates: you describe the behavior in a hardware description language —VHDL or Verilog— and a synthesis tool turns it into actual connections.
-- VHDL: an 8-bit counter. It is not a program: it is a circuit description.
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then cuenta <= (others => '0');
else cuenta <= cuenta + 1;
end if;
end if;
end process;The conceptual difference from C is enormous: here there are no instructions that run one after another. Everything described happens at once, on every clock edge. If you write ten processes, all ten run simultaneously, like ten separate circuits.
| Microcontroller | FPGA | |
|---|---|---|
| Execution | Sequential: one instruction at a time | Parallel: everything at the same time |
| Programmed in | C, assembly | VHDL, Verilog |
| Cost | Dollars | Tens to hundreds of dollars |
| Power consumption | Low | High |
| Strong at | Complex logic, arithmetic, communication, control | Many fast signals in parallel, video processing, high-speed acquisition |
| Typical example | Thermostat, control panel, instrument | Logic analyzer, image processing, software-defined radio |
If the problem fits in a microcontroller, use a microcontroller: it is cheaper, simpler and easier to maintain. An FPGA is justified when you need true parallelism or nanosecond timing: counting twenty encoders at once, processing video frame by frame, generating signals with single-clock-cycle precision. Choosing an FPGA “because it is more modern” usually ends in an expensive project that does the same thing as a two-dollar chip.
04In the lab
With an EPROM or SRAM on a breadboard, switches on the address lines and LEDs on the data lines, step through the locations and note down the contents. Drive CS̄ and OĒ by hand and observe what happens to the outputs when the chip is disabled: they go to high impedance, neither 1 nor 0.
With a 74HC138 and two memories, build the 64 KB map from the example. Use LEDs to check which chip is enabled according to A15. Then deliberately wire the two CS̄ lines together and observe on the oscilloscope the conflict on the data bus.
Write the same location of the microcontroller's EEPROM in a fast loop and keep count of the writes, displaying it on the serial port. Calculate how long it would take to reach a million cycles. Then write the same data rotating among 16 locations and compare the resulting service life.
If a board is available, describe the counter from the previous section in VHDL, synthesize it and watch it run on LEDs. Then duplicate the process to get two counters with different dividers and check that they run in parallel, with neither delaying the other. That experiment is the difference between hardware and software.
05Common mistakes
| Symptom | Usual cause |
|---|---|
| The data bus shows strange values | Two chips enabled at the same time: output conflict. Check the decoding. |
| The memory always reads the same thing | An address line was left unconnected or shorted, and several addresses point to the same location. |
| The write is not saved | WĒ and OĒ active at the same time, or the write time was not respected. |
| A value stored in EEPROM gets corrupted | Write interrupted by a voltage drop. Enable brown-out detection and do not write on every pass of the loop. |
| The USB flash drive “died” | Worn-out cells, or a corrupted allocation table from unplugging it during a write. |
| The FPGA does not start at power-up | It is volatile: it needs to load its configuration from the external Flash. If that Flash is not programmed, there is no circuit. |
| The VHDL design “gets the order wrong” | It was thought of as a sequential program. In hardware everything happens at once: the order of the lines does not define the order in time. |
06Self-assessment
How many address lines does an 8 K × 8 memory need?
8 K = 8192 = 213, so 13 lines (A0 to A12) and 8 data lines.
What is the difference between SRAM and DRAM?
SRAM stores each bit in a six-transistor flip-flop: it is fast and needs no maintenance, but it is expensive and not very dense. DRAM uses one capacitor per bit: it is dense and cheap, but it discharges and needs permanent refreshing.
What is the CS̄ signal for?
To enable the chip. It allows several memories to be connected to the same bus: address decoding activates only one at a time, and the others keep their outputs in high impedance.
Why does a NAND Flash withstand fewer cycles than an EEPROM?
Because it prioritizes density and cost: smaller cells, even storing several bits per cell. That wears the oxide more with each erase. EEPROM is much less dense but withstands on the order of a million cycles per byte.
What is wear leveling and where is it implemented?
Spreading the writes among all the blocks so that none wears out first. It is done by the controller inside the USB flash drive, card or SSD, with its own processor and its translation table.
What is inside an FPGA instead of gates?
Lookup tables (LUTs): very small memories that store the truth table of the desired function, with an associated flip-flop. Programming the FPGA means writing those tables and the connections between blocks.
What is the essential difference between programming in C and describing in VHDL?
In C the instructions run one after another; in VHDL you describe hardware that works all at the same time. Ten processes in VHDL are ten simultaneous circuits, not ten steps.
When is an FPGA better than a microcontroller?
When you need true parallelism or nanosecond timing: many fast signals handled at once, video processing, high-speed acquisition. For control, communication and moderate computation, the microcontroller is cheaper and simpler.
A CPLD works as soon as it is powered on and an FPGA does not. Why?
Because the CPLD's configuration is non-volatile and lives inside the chip, whereas the FPGA loads its configuration at startup from an external Flash memory. If that memory fails, the FPGA is left without a function.
Why does an EPROM have a little quartz window?
Because it is erased by exposing the chip to ultraviolet light, which discharges the floating gates of the cells. That is why, once programmed, the window is covered with a label: sunlight would erase it over time.