CMOS memories
One bit of main memory is about 150,000 electrons on a leaky capacitor. If no one replenishes them, in less than a second the 1 is read as a 0.
01Three ways to store a bit
All the memory of a present-day computer is made with MOS transistors, but in three very different ways, each with a different compromise between speed, density and permanence:
| SRAM | DRAM | Flash | |
|---|---|---|---|
| How it stores the bit | Two cross-coupled inverters | Charge on a capacitor | Charge trapped in the gate of a transistor |
| Transistors per bit | 6 | 1 plus a capacitor | 1, and several bits per transistor |
| Cell area | About 120 to 150 F² | 6 to 8 F² | 4 F² and less, stacked in 3D |
| When power is cut | Lost | Lost, and it also has to be refreshed | Retained for years |
| Access | Less than a nanosecond | Tens of nanoseconds | Microseconds to read, more to write |
| Where it is found | Registers and caches, inside the processor | Main memory | Solid-state drives, USB flash drives, program memory |
\( F \) is the minimum feature size of the technology: measuring cells in \( F^2 \) makes it possible to compare them across generations. The Electronics Technician program page on memories and programmable devices presents the types from the point of view of use; here we look at the cell.
02SRAM: two inverters that hold each other up
The six-transistor SRAM cell is two CMOS inverters connected in a ring, each driving the other, and two access transistors that connect the two nodes to a pair of bit lines when the word line is activated. The ring has two stable states, and as long as there is power it holds itself, with no refresh.
The design of the cell is a tug of war between reading and writing with the same transistors:
- Read stability: when reading, the node that stores a 0 is connected to a bit line precharged to \( V_{DD} \) and rises a little. If it rises too much, the cell flips by itself. That is why the pull-down NMOS is made wider than the access transistor, in a ratio of 1.2 to 2.
- Write: to change the state, the access transistor has to overpower the pull-up PMOS, which is made the narrowest of the three.
The cell's static noise margin is measured by superimposing the two transfer curves, one mirrored: the resulting plot is called a “butterfly”, and the side of the largest square that fits in its wings is the margin. With each generation the variation between transistors shrinks it, and today SRAM is among the hardest things to scale.
03DRAM: a leaky capacitor
The DRAM cell is one transistor and one capacitor. The bit is the charge on the capacitor: full at \( V_{DD} \) is a 1, empty is a 0. To read, the bit line is precharged to \( V_{DD}/2 \) and the transistor is opened: the cell capacitor shares its charge with the much larger capacitance of the bit line, which moves only slightly:
The read is destructive: after sharing the charge, the cell is left at an intermediate value, and the sense amplifier rewrites it in the same cycle. In addition, the capacitor loses charge through the leakage of the junction and of the off transistor. Each cell is read and rewritten periodically, the refresh: the JEDEC standard requires refreshing each cell at least every 64 ms, and every 32 ms above 85 °C, because the leakage doubles about every ten degrees.
A 20 fF cell at 1.2 V stores about 150,000 electrons. Maintaining that capacitance while the cell shrinks forced the construction of capacitors shaped like very tall cylinders, with high-k dielectrics.
A cell written with a 1 that loses charge through a constant leakage. The plot shows the signal the cell would deliver to the bit line if it were read at each instant; the sense amplifier needs at least 30 mV to decide. You choose the cell capacitance, the bit line capacitance and the leakage current.
04Flash: trapped charge
A flash cell is a MOS transistor with a second gate, a floating one, completely insulated within the oxide (or, in current versions, a nitride layer that traps charge). The electrons that are forced in there stay imprisoned for years, and their negative charge raises the threshold voltage of the transistor. Reading means asking whether the transistor conducts with a reference gate voltage.
| Operation | Mechanism |
|---|---|
| Programming in NOR | Hot-carrier injection: electrons accelerated in the channel jump the oxide barrier |
| Programming and erasing in NAND | Fowler–Nordheim tunneling through the oxide, with 15 to 20 V |
| Several bits per cell | 4, 8 or 16 threshold levels are programmed to store 2, 3 or 4 bits (MLC, TLC, QLC) |
| Wear | Each write cycle damages the oxide a little: from about 100,000 cycles in single-bit cells to a few thousand in four-bit ones |
When the planar cell could not be shrunk any further, NAND flash went vertical: today more than two hundred layers of cells are stacked in the same chip. The drive controller spreads out the writes, corrects errors and reserves spare blocks: without it, a multi-bit-per-cell flash would not be reliable.
05How an array is organized
The cells form a matrix: a row decoder activates a word line, all the cells in that row dump their contents onto their bit lines, and the sense amplifiers at the foot of each column detect differences of tens of millivolts. A column decoder chooses which of those bits come out. Precharge, activate, sense and rewrite is the sequence of each access, and its timings are those that appear in memory datasheets as latencies.
06Where it appears in electronics
| Case | The memory and why |
|---|---|
| Microcontroller | Flash for the program, SRAM for the variables |
| Computer | SRAM in the caches, DRAM in the modules, NAND flash in the drive |
| FPGA | The configuration in SRAM cells, which is lost at power-off |
| Equipment that cannot lose data | Fast nonvolatile memories (FRAM, MRAM) that write like an SRAM |
| Cameras and phones | Multi-bit-per-cell NAND flash, with its controller |
07In the lab
With two inverters of a 74HC04 connected in a ring, force the state with a 1 kΩ resistor to each node and verify that it stays memorized when the resistor is removed. Measure the minimum supply voltage at which the ring still retains the data.
Charge a 1 nF capacitor through a small-signal MOSFET used as a switch, open the switch and measure with a high-impedance oscilloscope how long it takes to lose half of the voltage. Estimate the leakage current.
In a microcontroller, read the memory map in the datasheet, locate the flash and the SRAM, and after compiling a program compare how much it takes up of each.
08Common mistakes
- Thinking that DRAM is “RAM that is not erased” while it is powered. Without refresh it is lost in fractions of a second.
- Confusing nonvolatile with eternal. Flash has a finite number of write cycles and the retention drops with wear and temperature.
- Believing that reading a DRAM does not alter it. The read is destructive and the data has to be rewritten.
- Comparing memories by capacity without looking at latency. A DRAM takes a hundred times longer to respond than an SRAM cache.
- Writing to a microcontroller's flash in a loop. It wears out in hours.
09Self-assessment
Why does SRAM not need refresh while DRAM does?
SRAM stores the data in two cross-coupled inverters that hold each other up as long as there is power; DRAM stores it as charge on a capacitor that leaks.
With \( C_s = 25 \) fF, \( C_{BL} = 100 \) fF and \( V_{DD} = 1.1 \) V, how much does the bit line move when a 1 is read?
\( 0.55 \times 25/125 = 110 \) mV.
Why is the pull-down NMOS of an SRAM cell wider than the access transistor?
So that during a read the node storing a 0 rises only slightly and the cell does not change state.
How many threshold levels does a TLC cell need?
Eight, because it stores three bits.
Why is DRAM refreshed more often at high temperature?
Because the leakage current grows with temperature, and the cell loses its charge sooner.
10Further reading
- Bruce Jacob, Spencer W. Ng and David T. Wang. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann, 2008. The reference on how a computer's memories work inside, from the cell to the system.
- Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolić. Digital Integrated Circuits: A Design Perspective. 2nd ed., Prentice Hall, 2003. The memories chapter: cells, sense amplifiers and array organization.
- Rino Micheloni, Luca Crippa and Alessia Marelli. Inside NAND Flash Memories. Springer, 2010. The flash cell, its programming mechanisms and the reliability problems.