CMOS inverter
Two transistors, one always off: that is the reason a processor with billions of gates can operate without melting.
01Two complementary transistors
The CMOS inverter is a PMOS between the supply and the output and an NMOS between the output and ground, with both gates tied to the input. With the input at 0, the PMOS conducts and the NMOS is off: the output sits at \( V_{DD} \). With the input at \( V_{DD} \), the reverse. In either state one of the two transistors is off and there is no current path between the supply and ground: the inverter at rest consumes nothing but leakage.
That property, more than any other, explains why CMOS replaced all the earlier logic families. A chip with billions of transistors would be impossible if each gate consumed at rest like a TTL gate. The equations of each transistor are those of the previous unit.
02The transfer characteristic
As the input is swept from 0 to \( V_{DD} \), the output passes through five regions depending on the region each transistor is in. At the extremes one is off and the output is exactly \( V_{DD} \) or 0; in the middle both conduct, both are in saturation and the gain is enormous: the output falls almost vertically. The point where the input and the output are equal is the switching threshold \( V_M \). With the long-channel model, equating the two saturation currents:
A symmetric inverter has its threshold in the middle and both noise margins equal. Making the PMOS smaller saves area and capacitance, at the cost of shifting \( V_M \) downward and making the rise slower.
03Noise margins
A gate has to interpret correctly an input that is somewhat contaminated. The points where the slope of the characteristic equals −1 separate the regions where noise is attenuated from the region where it is amplified; they are called \( V_{IL} \) and \( V_{IH} \):
A second virtue, just as important: the gain in the transition region is greater than 1, so a chain of gates regenerates the levels. A degraded signal returns to exactly 0 or \( V_{DD} \) after passing through a few gates.
An inverter with thresholds of 0.5 V in both transistors, \( \mu_n / \mu_p = 2.5 \) and a long-channel model with slight channel-length modulation. You choose the supply and the width ratio \( W_p / W_n \); the program solves for the output at each input by equating the two currents, and also plots the current flowing from the supply to ground.
04Delay
The output of an inverter drives a capacitance: the gates that follow it, the wiring and its own drain junctions. Changing state means charging or discharging that capacitance with the current of the conducting transistor, so the delay is approximately
To drive a large load (a bus, an output pin) a chain of inverters is used, each one wider than the previous. The optimal design makes the width grow by a factor close to 4 per stage, and the number of stages grows with the logarithm of the load.
05Power
Although it consumes nothing at rest, the inverter consumes every time it switches. There are three components:
The dynamic term explains the strategy of all low-power electronics: the power falls with the square of the voltage, so lowering \( V_{DD} \) is the most effective measure. With 1 fF per gate, 0.8 V, 3 GHz and an activity factor of 0.1, each gate consumes 0.19 µW; a hundred million gates, 19 W. With the end of Dennard scaling, leakage current became an important part of the total, and processors completely shut off the blocks they are not using.
06The inverter in real integrated circuits
| Topic | What you need to know |
|---|---|
| 4000 series | The first CMOS family, from 3 to 18 V, slow but with minimal consumption |
| 74HC and 74HCT | Fast CMOS with the pinout of the 74 series; the HCT accepts TTL input levels |
| Floating inputs | An unconnected CMOS input sits in the transition region: both transistors conduct, the gate oscillates and heats up |
| Latch-up | The P and N regions of the inverter form a parasitic thyristor which, triggered by an overvoltage on a pin, short-circuits the supply |
| Electrostatic discharge | Each pin has diodes to the supply and to ground that protect the gates |
The parasitic thyristor of latch-up is the same four-layer device as in the unit on multijunction devices, only here it appears without anyone wanting it.
07In the lab
With a 74HC04 powered at 5 V and at 3.3 V, sweep the input with a variable source and measure the output. Locate \( V_M \), \( V_{IL} \) and \( V_{IH} \) and compare them with those in the datasheet.
With an ammeter in the supply of the same integrated circuit, slowly sweep the input and measure the current spike in the transition region. Repeat with the input left floating.
Drive an inverter with a square wave from 100 kHz to 10 MHz with a 100 pF load and measure the average supply current. Verify that it grows in proportion to the frequency and estimate \( C_L \) from the slope.
08Common mistakes
- Making the PMOS the same width as the NMOS expecting symmetry. Holes are slower; the threshold shifts downward.
- Leaving inputs unconnected. The gate sits in the transition region, consumes power and can oscillate.
- Believing that CMOS does not consume. It does not consume at rest; while switching, the power grows with frequency and with \( V_{DD}^2 \).
- Driving a large load with a single minimum-size gate. The delay grows with the load; a chain of progressively larger inverters is used.
- Applying voltage to an input while the integrated circuit is unpowered. The protection diodes conduct and can trigger latch-up.
09Self-assessment
Why does the CMOS inverter not consume at rest?
Because in either of the two states one of the two transistors is off and there is no path between the supply and ground.
With \( \mu_n / \mu_p = 2.5 \) and equal thresholds, what width ratio puts \( V_M \) at \( V_{DD}/2 \)?
\( W_p / W_n = 2.5 \), so that \( k_p = k_n \).
By how much does the dynamic power drop if \( V_{DD} \) goes from 1.2 to 0.9 V?
To \( (0.9/1.2)^2 = 56 \) %: almost half.
What is latch-up?
The triggering of a parasitic thyristor formed by the P and N regions of the CMOS circuit, which short-circuits the supply until it is switched off.
Why does a chain of inverters regenerate logic levels?
Because the gain in the transition region is much greater than 1 and outside it is smaller: intermediate levels are pushed toward 0 or toward \( V_{DD} \) at each stage.
10Further reading
- Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolić. Digital Integrated Circuits: A Design Perspective. 2nd ed., Prentice Hall, 2003. The chapter on the CMOS inverter is the reference: transfer curve, margins, delay and power.
- Neil H. E. Weste and David Money Harris. CMOS VLSI Design: A Circuits and Systems Perspective. 4th ed., Addison-Wesley, 2011. Logical effort for sizing chains of gates, and the problems of real circuits.
- Adel S. Sedra and Kenneth C. Smith. Microelectronic Circuits. 7th ed., Oxford University Press, 2014. The inverter derived from the MOS curves, with numerical examples.