MOS transistor: long channel, short channel and scaling
With a 30 nm channel, the textbook MOS formula predicts five times more current than the transistor delivers. And the supply voltage of processors does not go below 0.7 V because of a thermodynamic limit: 60 mV per decade.
01The MOS capacitor and inversion
The MOS transistor is a capacitor with a semiconductor as one of its plates: a conducting gate, a very thin oxide and a P-type silicon substrate. A positive voltage on the gate first pushes holes away from the surface (depletion) and, if it keeps rising, attracts so many electrons that the surface of the P-type silicon starts to behave as N-type: this is inversion. That layer of electrons, only a few nanometers thick, is the channel that joins the N⁺ source and drain regions.
The gate voltage at which inversion appears is the threshold voltage:
With a 2 nm oxide, \( C_{ox} = 17.3 \) fF/µm²: almost the whole history of the MOS is that of making this capacitor larger and larger per unit area, because the channel charge, and with it the current, is proportional to \( C_{ox} \).
02The long-channel model
With an overdrive voltage \( V_{ov} = V_{GS} - V_{th} \), the channel charge per unit area is \( C_{ox} V_{ov} \), and the electrons drift from source to drain with the channel mobility. Integrating along the channel gives the quadratic model:
For small signals, \( g_m = \sqrt{2\, \mu_n C_{ox} (W/L)\, I_D} = 2 I_D / V_{ov} \). Compared with the bipolar, \( g_m / I_D = 2/V_{ov} \) versus \( 1/V_T \): with \( V_{ov} = 0.2 \) V the MOS gives 10 S/A and the bipolar 38.7. For the same current, the MOS amplifies less.
With \( V_{GS} < V_{th} \) the current does not disappear: it falls exponentially, as in a bipolar, \( I_D \propto e^{V_{GS}/(n V_T)} \). The subthreshold slope \( S = n V_T \ln 10 \) cannot go below 60 mV per decade at room temperature. For a transistor that is off to conduct a million times less than when it is on, a threshold of at least 360 mV is needed, and that number is the reason that the supply voltage of processors stopped falling near 0.7 V.
03Short channel
When the channel length drops to hundreds of nanometers, the quadratic model goes wrong for several reasons at once:
| Effect | What happens |
|---|---|
| Velocity saturation | The field along the channel exceeds \( 10^4 \) V/cm and the electrons stop accelerating: the current starts to grow with \( V_{ov} \) instead of \( V_{ov}^2 \), and no longer improves as \( 1/L \) |
| Drain-induced barrier lowering (DIBL) | The drain, very close to the source, lowers the channel barrier: the threshold falls as \( V_{DS} \) rises and the off-state current goes up |
| Threshold roll-off with \( L \) | Part of the depletion charge under the gate is supported by the source and drain, and the gate has less control |
| Hot carriers | High-energy electrons become embedded in the oxide and the transistor degrades with use |
| Gate tunneling leakage | With oxides thinner than 2 nm electrons tunnel through it; SiO₂ was replaced by hafnium oxide, with a higher dielectric constant, which gives the same \( C_{ox} \) with more thickness |
Velocity saturation is incorporated into the model with a critical field \( E_c = 2 v_{sat} / \mu_n \): the saturation current becomes
An NMOS with a 2 nm oxide, a channel mobility of 400 cm²/V·s, a saturation velocity of \( 10^7 \) cm/s and a threshold of 0.4 V. You choose the channel length and the gate voltage; the plot shows the current per micron of width according to the model with velocity saturation (solid) and according to the long-channel one (dotted). The oxide is held fixed to isolate the effect of the length.
04Dennard scaling and its end
In 1974 Robert Dennard and his colleagues at IBM showed that if all the dimensions and all the voltages of a MOS transistor are divided by the same factor \( \kappa \), and the doping levels are multiplied by it, the transistor works the same and improves in every respect:
| Quantity | Scales as |
|---|---|
| Dimensions \( L, W, t_{ox} \) and voltages | \( 1/\kappa \) |
| Doping | \( \kappa \) |
| Current per transistor | \( 1/\kappa \) |
| Gate delay | \( 1/\kappa \) |
| Power per transistor | \( 1/\kappa^2 \) |
| Transistors per area | \( \kappa^2 \) |
| Power per area | Constant |
That last row is what sustained Moore's law for thirty years: chips with twice as many transistors, faster, that gave off the same heat. It broke down around 2005, when the threshold voltage could no longer keep falling because of the 60 mV per decade limit and with it the supply voltage stalled. Since then the power per area grows with each generation, clock frequencies have stayed near 3 to 5 GHz, and the performance gains have come from adding more cores, not from making them faster.
05The technologies that followed
| Technology | Introduction | What it solves |
|---|---|---|
| Strained silicon | Intel, 90 nm, 2003 | Deforms the channel lattice to raise the mobility |
| High-k dielectric and metal gate | Intel, 45 nm, 2007 | More \( C_{ox} \) without tunneling leakage |
| FinFET (tri-gate) | Intel, 22 nm, 2011 | The channel is a fin surrounded by the gate on three sides: better control, less DIBL |
| Gate-all-around (nanosheets) | Samsung, 3 nm, 2022 | The gate completely surrounds the channel |
Node names (“7 nm”, “3 nm”) stopped being a physical measurement more than a decade ago: they are commercial labels for the generation, and the actual gate length is considerably larger.
06Where it appears in electronics
| Case | What matters about the MOS |
|---|---|
| Processors and memories | Density, current per micron and off-state current |
| Integrated analog circuits | \( g_m/I_D \), intrinsic gain and matching; channels longer than the minimum are used |
| Power MOSFETs | Vertical structures with on-resistance of milliohms |
| CMOS image sensors | One photodiode and four transistors per pixel |
| Electrostatic discharge protection | The nanometer-thick oxide is punctured by a few volts: that is why pins have protection diodes |
07In the lab
With a small-signal MOSFET (2N7000 or BS170), measure \( I_D \) in saturation for five values of \( V_{GS} \). Plot \( \sqrt{I_D} \) against \( V_{GS} \): the line crosses the axis at \( V_{th} \) and its slope gives the transconductance parameter.
With the same transistor, measure currents between 10 nA and 10 µA with \( V_{GS} \) below the threshold and obtain the slope in mV per decade. Compare it with the 60 mV limit.
In a simulator with BSIM models of a 180 nm technology, plot \( I_D \) against \( V_{GS} \) in saturation for \( L \) of 180 nm and 2 µm. Verify which one follows a parabola and which one a straight line.
08Common mistakes
- Using the quadratic model in a short-channel transistor. It overestimates the current by a factor of several.
- Confusing \( V_{th} \) with \( V_T \). One is the threshold, hundreds of millivolts; the other the thermal voltage, 25.85 mV.
- Believing that a transistor that is off does not conduct. Subthreshold current is most of the standby consumption of a modern chip.
- Reading the node name as a length. “3 nm” is a commercial label.
- Handling gates without protection. An electrostatic discharge punctures the oxide.
09Self-assessment
What is inversion in a MOS capacitor?
The accumulation, under the gate, of so many minority carriers that the surface of the substrate changes type and forms a conducting channel.
In a long channel, how does the saturation current change when \( V_{ov} \) is doubled? And with extreme velocity saturation?
In a long channel it is quadrupled; with extreme velocity saturation, it is doubled.
Why can the subthreshold slope not be less than 60 mV per decade at 300 K?
Because the current is carried by carriers that surmount a barrier through thermal agitation, with a Boltzmann distribution: \( V_T \ln 10 = 59.5 \) mV is the minimum per decade.
According to Dennard, what happens to the power per area when scaling?
It stays constant, because the power of each transistor falls as \( 1/\kappa^2 \) and the number per area rises as \( \kappa^2 \).
What problem did the high-k dielectric solve?
The tunneling leakage of very thin oxides: it gives the same capacitance per area with a greater physical thickness.
10Further reading
- Yuan Taur and Tak H. Ning. Fundamentals of Modern VLSI Devices. 2nd ed., Cambridge University Press, 2009. The reference book on the modern MOSFET: short channel, scaling and their limits.
- Chenming Calvin Hu. Modern Semiconductor Devices for Integrated Circuits. Pearson, 2010. Written by one of the authors of the FinFET and of the BSIM model, with velocity saturation and DIBL clearly explained.
- Robert H. Dennard et al. Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions. IEEE Journal of Solid-State Circuits, 1974. The original paper on the scaling rules.