Microelectronic technology
Quadrupling the area of a chip, from 100 to 400 mm², multiplies its cost by six: four times fewer fit on the wafer and, besides, a smaller proportion comes out good.
01From silicon to the wafer
An integrated circuit is fabricated on a monocrystalline silicon wafer, sliced from an ingot grown from molten silicon by the Czochralski method. Current wafers are 200 or 300 mm in diameter and less than a millimeter thick, and are polished until the surface is flat on the atomic scale. The whole process takes place in clean rooms, because a particle the size of a transistor is enough to ruin a chip. Hundreds or thousands of identical chips are fabricated at once on each wafer.
02The processes
| Process | What it does |
|---|---|
| Photolithography | Transfers the pattern of a mask to a photosensitive resist, with 193 nm deep ultraviolet or 13.5 nm extreme ultraviolet light |
| Oxidation | Grows silicon dioxide on the wafer, gate and isolation insulator |
| Ion implantation and diffusion | Introduce dopants into defined areas to form n and p regions |
| Deposition (CVD, PVD) | Adds layers of polysilicon, dielectrics and metals |
| Etching | Removes material where the resist does not protect it; dry, with plasma, for vertical walls |
| Chemical-mechanical polishing (CMP) | Planarizes each layer so the next one can be stacked |
A CMOS process repeats those steps dozens of times: it forms the n and p wells, isolates the transistors with oxide trenches, grows the gate oxide and defines the gates, implants source and drain, and then builds on top eight to more than ten layers of copper interconnect separated by dielectrics. The first part, which makes the transistors, is the front end; the interconnect part, the back end. Besides CMOS there are bipolar processes, BiCMOS, silicon-on-insulator (SOI) and compound semiconductors such as gallium arsenide and gallium nitride. Circuit design for these processes was covered in analog integrated circuit design.
03Testing, dicing and packaging
Once the wafer is finished, each chip is tested with a probe card and the defective ones are marked. Then the wafer is diced and the good chips are packaged: they are bonded to a lead frame or substrate and connected with gold or copper wires (wire bonding) or flipped over onto solder balls (flip chip). Packages evolved from through-hole to surface mount and to maximum density:
| Package | Characteristics |
|---|---|
| DIP | Through-hole, leads every 2.54 mm |
| SOIC, TSSOP | Surface mount with leads on two sides |
| QFP | Leads on all four sides; many pins, but fragile |
| QFN | No protruding leads, with a thermal pad underneath |
| BGA | Array of solder balls over the whole underside |
| CSP and wafer-level package | The size of the chip itself |
04Manufacturing yield
Defects are spread at random over the wafer with a density \( D \) per unit area. A chip of area \( A \) comes out good if it has no defects at all; with a Poisson distribution, and with the Murphy model, which assumes a variable density and fits the data better:
The yield as a function of chip area, with the Poisson model (blue) and the Murphy model (green), for the chosen defect density. The panel computes the chips per wafer, the good ones and the cost of each good chip with the Murphy model.
That is why large chips are divided into several smaller ones, chiplets, which are tested separately and mounted together in a single package.
05In the lab
Observe an opened integrated circuit under a microscope: identify the bond pads, the wires and the blocks of the chip.
Compare the junction-to-ambient thermal resistance of the same circuit in SOIC, QFN with a thermal pad and BGA.
With this page's lab, estimate how worthwhile it is to split a 400 mm² chip into four 100 mm² ones.
06Common mistakes
- Thinking that the chip cost grows with the area. It grows faster, because the yield falls.
- Forgetting the edge of the wafer. Large chips waste more surface at the perimeter.
- Confusing the technology node with a physical measurement. Today the node name no longer matches any dimension of the transistor.
- Choosing the package by size alone. It decides the heat dissipation, the lead inductance and whether the joints can be inspected.
07Self-assessment
How many 100 mm² chips fit on a 300 mm wafer?
About 640.
With 0.1 defects per cm², what yield does the Poisson model give for that chip?
\( e^{-0.1} \approx 0.905 \).
What is chemical-mechanical polishing for?
To planarize each layer so the next one can be stacked with lithographic precision.
What advantage does a BGA have over a QFP?
Many more leads in less area, short connections and better heat dissipation; in exchange, the joints can only be inspected with X-rays.
08Further reading
- Richard C. Jaeger. Introduction to Microelectronic Fabrication. 2nd ed., Prentice Hall, 2002. The fabrication processes explained step by step.
- Stephen A. Campbell. Fabrication Engineering at the Micro- and Nanoscale. 4th ed., Oxford University Press, 2013. The physics and engineering of each step of the process.
- Peter Van Zant. Microchip Fabrication. 6th ed., McGraw-Hill, 2014. A practical view of the industry, with yield and costs.