Analog integrated circuit design
On a chip, no resistor is worth what the drawing says, but two neighboring resistors are almost identical. All integrated analog design rests on that paradox.
01Designing with ratios
Integrated analog design starts from a paradox. The absolute values on a chip are poor: a resistor can come out 20 % above or below its value, the threshold voltage of a transistor varies by tens of millivolts from one wafer to another, and no capacitance is exact. But two identical components, drawn together on the same chip, are almost identical: their ratio holds to within tenths of a percent.
That is why analog integrated circuits are designed to depend on ratios and not on values: the gain as a ratio of two resistors, the current of a mirror as a ratio of two geometries, the split of a differential pair as the difference between two twin transistors. What limits precision is no longer the tolerance, but the mismatch.
02Mismatch and Pelgrom's law
Even when drawn identical, two transistors differ because of random effects at the atomic scale: the exact number of dopant atoms under each gate, the irregularities of the edge. Marcel Pelgrom showed in 1989 that the spread of the difference between two transistors falls with the square root of their area:
The consequence is a direct trade-off between precision and area: to cut the offset in half you have to quadruple the area of the input transistors, with more capacitance, less speed and more cost. In a MOS differential pair, the input offset combines the two sources:
4000 MOS differential pairs are virtually fabricated, each with random mismatches according to Pelgrom's law, and the distribution of their offset voltage is plotted. You choose the area of the input transistors, the overdrive voltage and the offset specification the chip must meet.
03The drawing matters as much as the schematic
Besides random mismatch, there are systematic errors that the drawing of the chip (the layout) can avoid: gradients of temperature, oxide thickness or mechanical stress across the wafer. The classic techniques:
- Common centroid: each transistor of the pair is split into parts that are laid out in a cross, so that a linear gradient affects both equally.
- Interdigitated: the fingers of the two transistors alternate, A B A B.
- Dummy elements: inactive transistors or resistors at the ends, so that the active ones all have the same surroundings.
- Same orientation and symmetry: all matched devices in the same direction, with the same routing of connections, far from the edges and symmetric with respect to heat sources.
04Designing with \( g_m/I_D \)
In a modern technology the long-channel equations are unreliable, and the design is organized around one number: the efficiency \( g_m/I_D \), how much transconductance each ampere gives. It defines which region the transistor operates in:
| Region | \( g_m/I_D \) | What you gain | What you lose |
|---|---|---|---|
| Weak inversion | Up to about 25 S/A, near the limit \( 1/nV_T \) | Maximum gain per unit current, minimum power consumption | Speed and area |
| Moderate inversion | 10 to 20 S/A | A good balance | — |
| Strong inversion | Less than 10 S/A | Speed, linearity, better current matching | Power consumption and output swing |
The designer chooses \( g_m/I_D \) for each transistor according to what is needed, obtains the current from the required \( g_m \), and the width comes from measured or simulated tables of the technology.
05A two-stage operational amplifier
The most widely taught architecture brings together everything in this course: a differential pair with a mirror as an active load, a common-source gain stage and a capacitor \( C_c \) between the input and the output of the second stage which, through the Miller effect, sets a dominant pole and makes the amplifier stable with feedback. Its two key figures come directly from the first stage:
06The design flow
- Specification: gain, bandwidth, noise, offset, power consumption, area.
- Schematic and sizing, with \( g_m/I_D \) or with equations.
- Simulation with the foundry models, at all process, voltage and temperature corners, and with Monte Carlo for the mismatch.
- Layout, with the matching techniques.
- Verification: design rules (DRC), layout versus schematic (LVS) and extraction of the parasitics to simulate again.
- Sending to fabrication and measuring the samples.
07In the lab
Measure the offset voltage of ten operational amplifiers of the same model and compare the spread with the typical and maximum values given in the datasheet.
In a simulator with models of a CMOS technology, run a Monte Carlo analysis of a differential pair for two different areas and verify that the spread scales as \( 1/\sqrt{WL} \).
With a free layout tool, draw a 2 × 2 common-centroid differential pair and a simple one, and explain which gradient each one cancels.
08Common mistakes
- Designing with absolute values. In an integrated circuit, only ratios are reliable.
- Using minimum-size input transistors. The offset grows as the inverse of the square root of the area.
- Simulating only the typical case. A circuit has to work at all the corners and across the whole spread.
- Leaving the layout for last. A drawing without symmetry ruins a good schematic.
09Self-assessment
How much area is needed for \( \sigma(\Delta V_{th}) = 1 \) mV with \( A_{VT} = 4 \) mV·µm?
\( WL = (4/1)^2 = 16 \) µm².
What happens to the offset if the area is quadrupled?
It is cut in half.
What problem does the common centroid solve?
Linear gradients across the chip, which affect both transistors of the pair equally.
What is the slew rate with \( I_{SS} = 40 \) µA and \( C_c = 4 \) pF?
\( 40\text{ µA} / 4\text{ pF} = 10 \) V/µs.
10Further reading
- Behzad Razavi. Design of Analog CMOS Integrated Circuits. 2nd ed., McGraw-Hill, 2017. The two-stage amplifier, compensation and analog layout.
- Alan Hastings. The Art of Analog Layout. 2nd ed., Prentice Hall, 2005. The reference on matching and layout techniques.
- Paul G. A. Jespers and Boris Murmann. Systematic Design of Analog CMOS Circuits Using Pre-Computed Lookup Tables. Cambridge University Press, 2017. The \( g_m/I_D \) method explained by its leading advocates.
- Marcel J. M. Pelgrom, Aad C. J. Duinmaijer and Anton P. G. Welbers. Matching Properties of MOS Transistors. IEEE Journal of Solid-State Circuits, 1989. The original paper on the matching law.