Applied Electronics III · 120 h · Topic 2 of 10

Frequency synthesis

With 1 kΩ in the filter, a PLL takes 645 μs to change channel; with 3.3 kΩ, 205 μs. A single resistor decides whether the loop oscillates before locking.

Direct synthesis Charge-pump PLL Loop filter Damping Lock time

01How a frequency is synthesized

A transmitter or a receiver needs local oscillators that change channel with the accuracy of a crystal. There are three families of synthesizers, which are combined in real equipment:

Technique	Idea	Advantage	Limit
Analog direct synthesis	Mix, multiply and divide reference frequencies	Very fast switching	Bulky and with spurs
Direct digital synthesis (DDS)	A phase accumulator and a converter	Very fine resolution, instantaneous change	Frequency below half the clock
Phase-locked loop (PLL)	A VCO locked to a reference through a divider	GHz frequencies with low noise	The loop takes time to lock

Direct digital synthesis was covered in signal sources, and the architecture of the integer-N and fractional-N PLL, with its phase noise, in synthesized generators. Here the dynamics of the loop are studied: how long it takes to change channel and how the filter is chosen.

02The linear model of the charge-pump PLL

Once locked, the PLL is a phase control system. The charge-pump phase detector delivers a current proportional to the phase error, \( K_\phi = I_{cp}/2\pi \); the loop filter, a resistor in series with a capacitor, converts it to a voltage; the VCO converts it to frequency, and since phase is the integral of frequency, the VCO behaves as an integrator \( K_v/s \). With the divider \( N \), the loop gain has two poles at the origin and a zero:

\[ G(s) = \frac{K_\phi K_v (1 + sRC)}{N C\, s^2} \] \[ \omega_n = \sqrt{\frac{K_\phi K_v}{N C}} \] \[ \zeta = \frac{R C\,\omega_n}{2} \] It is a type 2 loop: it follows a frequency change with no phase error, as seen in steady state. \( \omega_n \) and \( \zeta \) set the loop bandwidth and the shape of the lock. In practice a second capacitor is added in parallel to filter the charge-pump pulses, which adds a high pole.

03Lock time and trade-offs

When the channel changes, the divider changes its N and the VCO frequency goes from the old value to the new one with the step response of the closed loop. The lock time is of the order of a few time constants \( 1/(\zeta\omega_n) \): a wide loop locks quickly. But the bandwidth has limits. It has to be much smaller than the comparison frequency, so that the loop is stable and attenuates the reference spurs. And it decides the phase noise: inside the band the reference's noise multiplied by N dominates, outside, that of the VCO.

Lab · the locking of a PLL

A synthesizer with a 50 MHz/V VCO, N = 2400 and comparison at 1 MHz, changing channel with a 1 MHz jump. The curve is the VCO frequency relative to the new channel; it is considered locked when it stays within ±1 kHz of the channel, marked by the green strip.

Filter resistance R =

04In the lab

Activity 1 · Measured lock

With an integrated PLL, measure the VCO control voltage with an oscilloscope when jumping channel and compute the lock time for two values of R.

Activity 2 · Reference spurs

Observe on the spectrum analyzer the spurs at ±f_PFD from the carrier and how they change when adding the filter's second capacitor.

Activity 3 · Filter design

Compute the loop filter with the PLL manufacturer's tool for 50 kHz of bandwidth and 50° of phase margin, and compare with the measurement.

05Common mistakes

Seeking the widest possible loop. It lets through the reference noise and the comparison spurs.
Forgetting that ω_n depends on N. When changing channel over a wide range, the bandwidth and the damping change.
Using a damping ratio of 0.707 as a rule. With the filter zero, the overshoot is greater than in a pure second-order system.
Ignoring the VCO gain over its whole range. K_v varies, and with it the dynamics.

06Self-assessment

What K_φ does a 2 mA charge pump have?

\( 2\cdot10^{-3}/2\pi \approx 318 \) μA/rad.

If C is quadrupled while keeping R, how do ω_n and ζ change?

ω_n is halved; ζ is doubled, because it is proportional to C·ω_n.

Why does the charge-pump PLL follow a frequency change with no phase error?

Because its loop gain has two integrators: that of the VCO and that of the filter capacitor.

What limits the loop bandwidth from above?

The comparison frequency: the loop has to be much slower, for stability and to filter the spurs.

07Further reading

Dean Banerjee. PLL Performance, Simulation, and Design. 5th ed., Dog Ear Publishing, 2017. Loop filter design and lock time, with working formulas.
Floyd M. Gardner. Phaselock Techniques. 3rd ed., Wiley, 2005. The classic PLL theory, including the charge-pump comparator.
Behzad Razavi. RF Microelectronics. 2nd ed., Prentice Hall, 2011. Frequency synthesizers in integrated transceivers.