Synthesized signal generators
For 1 MHz channels at 2.4 GHz, an integer-N synthesizer multiplies the phase noise of its comparator by 2440. A fractional one, by 49: its phase noise ends up 17 dB lower.
01From the DDS to the phase-locked loop
Direct digital synthesis in the signal sources of Measurements I gives very fine resolution, but its output cannot exceed a fraction of the clock. To generate signals from hundreds of megahertz to several gigahertz with the accuracy of a crystal, RF generators use a phase-locked loop (PLL): a voltage-controlled oscillator (VCO) whose frequency, divided by \( N \), is compared with a stable reference. The loop corrects the VCO until the two coincide:
02The building blocks of the synthesizer
| Block | Function |
|---|---|
| Reference | A temperature-compensated (TCXO) or oven-controlled (OCXO) crystal oscillator, sometimes locked to GPS |
| R divider | Lowers the reference to the comparison frequency |
| Phase-frequency detector with charge pump | Delivers current pulses proportional to the phase error |
| Loop filter | Integrates the pulses and sets the loop bandwidth and its stability |
| VCO | Generates the output; its frequency depends on the control voltage |
| N divider | Brings the output down to the comparison frequency |
The PLL is a feedback system, and its bandwidth and phase margin are designed like those of a feedback amplifier. For stability, the loop bandwidth is kept below one tenth of \( f_{PFD} \): comparing at a low frequency forces a slow loop, which takes a long time to lock when the channel changes.
03Phase noise
A real generator does not produce a perfect spectral line: its phase fluctuates, and the spectrum has "skirts" on both sides of the carrier. Phase noise is specified in dBc/Hz at an offset from the carrier. Within the loop bandwidth, the noise of the reference and of the detector is multiplied by \( N \), that is, it rises \( 20 \log N \); outside it, the VCO noise dominates. The in-band noise is estimated with the detector’s figure of merit, about −220 dBc/Hz in current circuits:
That is the reason for fractional-N synthesizers: the divider alternates between \( N \) and \( N+1 \) with a sigma–delta modulator, so that the average is fractional. The comparison is made at tens of megahertz and a step of a few hertz is obtained. The price is the fractional spurs, lines close to the carrier that the modulator and the loop filter have to keep low.
A synthesizer for the 2.4 GHz band with a figure of merit of −220 dBc/Hz. In integer-N, the comparison frequency is the channel step; in fractional-N, 50 MHz. The bars compare the in-band phase noise of the two architectures.
04How to read the datasheet of a synthesized generator
- Frequency range and resolution, and the accuracy, which is that of the internal or external reference.
- Phase noise at 10 kHz or 20 kHz from the carrier, the figure that separates a laboratory generator from a high-purity one.
- Spurs and harmonics, in dBc.
- Switching time between frequencies, which depends on the loop bandwidth.
- Output level and its accuracy, and the available modulations: AM, FM, pulse, I/Q.
05In the laboratory
Use a spectrum analyzer to measure the phase noise of a synthesized generator at 1 kHz, 10 kHz and 100 kHz from the carrier, correcting for the resolution bandwidth.
Program an integrated PLL synthesizer with a microcontroller, in integer-N and in fractional-N, and compare the output spectrum and the spurs.
Lock the laboratory’s generator and counter to the same 10 MHz reference and observe how the reading difference disappears.
06Common mistakes
- Comparing at the channel step frequency without need. It raises the phase noise and makes the loop slow.
- Forgetting that the reference noise is multiplied. A noisy reference ruins a GHz synthesizer.
- Ignoring the fractional-N spurs. They can fall inside the adjacent channel.
- Reading the analyzer’s phase noise without correcting for its bandwidth. It is expressed per hertz.
07Self-assessment
What N is needed to synthesize 915 MHz comparing at 200 kHz?
4575.
How much does the in-band phase noise rise when multiplying by 1000?
\( 20 \log 1000 = 60 \) dB.
Why can a fractional synthesizer have a faster loop?
Because it compares at a much higher frequency, and the loop bandwidth can be proportionally greater.
What is the disadvantage of fractional-N?
The fractional spurs close to the carrier.
08Further reading
- Dean Banerjee. PLL Performance, Simulation, and Design. 5th ed., Dog Ear Publishing, 2017. The design of charge-pump synthesizers, with phase noise and spurs.
- Ulrich L. Rohde. Microwave and Wireless Synthesizers: Theory and Design. Wiley, 1997. The classic reference on radio-frequency synthesizers.
- Roland E. Best. Phase-Locked Loops: Design, Simulation, and Applications. 6th ed., McGraw-Hill, 2007. Analog and digital PLLs from the standpoint of control theory.