Digital signals, logic analyzers and electromagnetic compatibility
Two identical 25 MHz clocks emit very differently at 300 MHz if one has 1 ns edges and the other 5 ns. What decides the high emissions is the rise time, not the frequency.
01The logic analyzer
A digital system has dozens of lines changing at once. The oscilloscope shows a few with analog detail; the logic analyzer shows many, 16, 32 or more, but only as zeros and ones, comparing each input with a threshold. It works in two modes:
| Mode | Sampling clock | What it is for |
|---|---|---|
| Timing | Internal, asynchronous, several times faster than the signal | Seeing timing relationships, spurious pulses, setup-time violations |
| State | The system’s own clock | Seeing what values the buses held in each cycle, as the circuit sees it |
In timing mode, the resolution is the sampling period: to see an edge with an error of 10% of the signal’s period you have to sample at least ten times faster. Mixed-signal analyzers and oscilloscopes decode protocols (UART, SPI, I²C, CAN, USB) and trigger on contents, as seen in serial protocols. For fast links, the tool is the eye diagram from digital modulation.
02Electromagnetic compatibility
A device is electromagnetically compatible if it works well in its environment without disturbing others. Electromagnetic compatibility (EMC) has two faces: emissions, what the device produces, and immunity, what it withstands. Each is divided into conducted, through the cables, and radiated, through the air:
| Test | Typical range | How it is measured |
|---|---|---|
| Conducted emissions | 150 kHz to 30 MHz | With a line impedance stabilization network (LISN) between the mains and the device |
| Radiated emissions | 30 MHz to 1 GHz and beyond | With antennas at 3 or 10 m, in a semi-anechoic chamber or open-area test site |
| Immunity | Electrostatic discharges, fast transients, RF fields, surges | Applying the disturbance and verifying operation |
The emission limits for multimedia equipment are in the CISPR 32 standard. For residential use, class B, the radiated emissions measured at 10 m must not exceed 30 dBμV/m between 30 and 230 MHz, nor 37 dBμV/m between 230 MHz and 1 GHz, with a quasi-peak detector. Preliminary measurements in the development laboratory, with a spectrum analyzer and near-field probes, save repeating costly formal tests.
03The spectrum of a clock
The most common source of emissions in a digital circuit is its clock. An ideal square wave has odd harmonics that decrease 20 dB per decade; a real one, with edges of finite duration, is a trapezoid. Its spectral envelope has two breakpoints:
The harmonics of a clock with a 50% duty cycle, in dBμV, and its envelope. The shaded zone is the radiated emissions band from 30 MHz to 1 GHz.
The measures that follow from this result are those of design for EMC: edges no faster than necessary, series resistors on clock outputs, continuous ground planes that shorten the current loops, and decoupling capacitors close to each integrated circuit.
04In the laboratory
Capture an SPI bus with a logic analyzer in both modes and compare what is seen in each.
Scan a microcontroller board with a near-field probe connected to a spectrum analyzer and find the source of the clock harmonics.
Add a 33 Ω resistor in series with the clock output and measure the reduction of the high harmonics.
05Common mistakes
- Sampling in timing mode only slightly faster than the signal. Pulses are missed and the position of the edges is imprecise.
- Thinking that lowering the clock frequency reduces all the emissions. The high ones are set by the rise time.
- Leaving EMC for the final test. Fixing a finished design is expensive; it is prevented in the layout.
- Confusing the near-field probe measurement with the standards test. It is for comparing, not for certifying.
06Self-assessment
Where is the second breakpoint of the envelope of a clock with 2 ns edges?
\( 1/(\pi \cdot 2\cdot10^{-9}) \approx 159 \) MHz.
How much does the envelope fall between 300 MHz and 1 GHz if the second breakpoint is at 100 MHz?
40 dB per decade: about 21 dB.
What radiated emission limit does CISPR 32 class B set at 100 MHz, measured at 10 m?
30 dBμV/m quasi-peak.
What is the difference between state mode and timing mode?
In state mode, sampling is done with the system clock; in timing mode, with a faster internal clock.
07Further reading
- Clayton R. Paul. Introduction to Electromagnetic Compatibility. 2nd ed., Wiley, 2006. The spectrum of digital signals, emissions and interference reduction.
- Henry W. Ott. Electromagnetic Compatibility Engineering. Wiley, 2009. Design for compatibility: grounds, shields, filters and board layout.
- Keysight Technologies. Feeling Comfortable with Logic Analyzers. Application Note 1337, Keysight. The state and timing modes and triggering in logic analyzers.