Serial communications and protocols
A CAN frame carries at most 8 data bytes and 47 control bits. That is why, even at 1 Mbit/s, a car’s bus carries no more than about 72 kB/s of useful data.
01Why almost everything is serial
For decades data traveled in parallel: eight, sixteen or thirty-two lines at a time. At high speed that stops working: the bits of a single data word arrive with timing differences because of the different lengths of the traces, and every line that switches adds noise to its neighbors. A single differential line, properly matched, reaches tens of gigabits per second today. That is why USB, SATA, PCI Express and Ethernet replaced their parallel predecessors, and on the board, two or three wires of a serial bus replace an entire data bus.
The fundamental difference is how the receiver knows when to read each bit. In a synchronous link a separate clock travels along; in an asynchronous one, the two ends agree on the speed and synchronize with a start bit; in fast links, the clock is embedded in the data and the receiver recovers it. The circuits are presented in the technician program, in serial communication and serial buses.
02Inside the board: UART, SPI and I²C
| UART | SPI | I²C | |
|---|---|---|---|
| Lines | TX and RX | SCLK, MOSI, MISO and one select per slave | SDA and SCL, open-drain with pull-up resistors |
| Clock | Asynchronous, agreed speed | Synchronous, generated by the master | Synchronous, generated by the master |
| Typical speed | 9600 to 1 Mbit/s | 1 to 50 MHz | 100 kHz, 400 kHz or 1 MHz |
| Devices | Two | One per select line | Up to 127, by 7-bit address |
| Overhead | Start and stop per byte | None | Address and an acknowledge bit per byte |
The UART tolerates a limited speed difference between the two ends: the receiver samples at the center of each bit counting from the start edge, and by the tenth bit the accumulated error cannot exceed half a bit. In practice, the sum of the errors of the two clocks must stay below about 4 %, which sometimes rules out the internal RC oscillator.
In I²C, the lines are pulled low actively and rise through the pull-up resistors. The rise time, which the standard limits, sets the maximum value of the resistor:
03Fieldbuses: CAN and RS-485
Outside the board, between pieces of equipment, buses use differential signals: two twisted wires that carry the signal and its opposite, so that noise that affects both equally is canceled at the receiver. RS-485 defines only the electrical layer, for up to 32 unit loads over 1200 m. CAN, designed for cars, adds a complete protocol:
- Nondestructive arbitration. The 0 bit is dominant: if two nodes transmit at the same time, the one sending a 1 and reading a 0 backs off without losing anything. The lowest identifier wins, which is the one with the highest priority.
- Bit stuffing. After five identical bits an opposite one is inserted, so that there are enough edges to resynchronize the clocks. The frame length depends on the data.
- Error detection. 15-bit CRC, acknowledgment by all receivers, and counters that disconnect a faulty node.
\( n \) bytes are sent over the chosen protocol. The chart shows the first bits of the frame, with its fields (the first data byte is 0x4B), and below, how much of the frame is useful data. In CAN, the identifier is 0x123 and the real stuffing is calculated together with the CRC.
04High speed
Above a few hundred megabits per second, each link is a differential transmission line of controlled impedance, typically 90 or 100 Ω, terminated at the receiver. LVDS uses a swing of just 350 mV, which switches fast and consumes little. The clock does not travel separately: it is encoded in the data to guarantee transitions, and the receiver recovers it with a PLL.
| Link | Speed per lane | Encoding | Efficiency |
|---|---|---|---|
| USB 2.0 high speed | 480 Mbit/s | NRZI with bit stuffing | Depends on the data: in the worst case, one extra bit every six |
| PCI Express 2.0 and USB 3.0 | 5 Gbit/s | 8b/10b | 80 % |
| PCI Express 3.0 | 8 Gbit/s | 128b/130b | 98.5 % |
| Ethernet 10GBASE-R | 10.3 Gbit/s | 64b/66b | 97 % |
The quality of a fast link is evaluated with the eye diagram: all the bits synchronized with the recovered clock are superimposed on the oscilloscope. An open eye means that the receiver tells zeros from ones well; noise, jitter and reflections close it.
05Where it appears in electronics
| Application | Typical bus |
|---|---|
| Temperature sensor or accelerometer on a board | I²C or SPI |
| Display or external flash memory | SPI, or QSPI with four data lines |
| Microcontroller debug console | UART |
| Automobile, agricultural machinery | CAN and CAN FD |
| Industrial automation | RS-485 with Modbus, or industrial Ethernet |
| Graphics card, solid-state drive | PCI Express |
06In the lab
With a logic analyzer, capture an I²C transaction with a sensor and an SPI one with a memory. Identify the address, acknowledgments and data, and measure the real clock speed.
Measure the rise time of SDA with pull-ups of 10 kΩ, 4.7 kΩ and 1 kΩ, and verify which one meets the standard at 400 kHz.
Build a CAN bus with two microcontrollers and their transceivers, with 120 Ω terminations. Send frames with different identifiers at the same time and observe the arbitration.
07Common mistakes
- Forgetting the I²C pull-ups, or adding too many. Each module brings its own, and in parallel they lower the resistance so much that the devices cannot pull the line low.
- Mixing up the SPI mode. The clock polarity and phase have to match on master and slave; otherwise the data arrives shifted by one bit.
- Not terminating a CAN or RS-485 bus. Without the resistors at the ends, reflections corrupt the bits.
- Calculating the time of a CAN frame without the stuffing. In the worst case it adds 24 bits to a 111-bit frame: almost 22 %.
08Self-assessment
How long does it take to send one byte over 8N1 UART at 115,200 bit/s?
10 bits: 86.8 µs.
How many bits does writing 2 bytes to a device take in I²C?
Start, 9 address bits and 9 per byte, and stop: \( 9 \cdot 3 + 2 = 29 \).
Two CAN nodes transmit identifiers 0x120 and 0x123 at the same time. Which one wins?
0x120, the lower one: at the first bit where they differ it sends a dominant 0.
What efficiency does 8b/10b encoding have?
80 %: for every 8 data bits, 10 are transmitted.
09Further reading
- NXP Semiconductors. UM10204: I²C-bus Specification and User Manual. Rev. 7, 2021. The I²C bus standard, with the timing, the speeds and the calculation of the pull-up resistors.
- Wilfried Voss. A Comprehensible Guide to Controller Area Network. 2nd ed., Copperhill, 2005. CAN explained from the physical layer to error handling.
- Howard Johnson and Martin Graham. High-Speed Signal Propagation: Advanced Black Magic. Prentice Hall, 2003. Fast serial links as a problem of transmission lines, losses and equalization.