Introduction to analog integrated circuit design
A 2 pF capacitor sets the bandwidth of an integrated op amp and creates a zero that steals phase from it. A 1/gm resistor in series makes it disappear.
01From the specification sheet to silicon
Designing an analog integrated circuit means sharing out a budget: with a limited current and area you have to obtain gain, bandwidth, phase margin, output swing, noise and offset. Applied Electronics I introduced the basics, matching, Pelgrom's law and design with \( g_m/I_D \), in analog integrated circuit design. Here we go through the design of a complete block using everything seen in the subject: feedback, frequency response and compensation.
| Stage | What is decided | Tool |
|---|---|---|
| Specification | Gain, GBW, phase margin, slew rate, power, swing | The system that uses the block |
| Topology | One or two stages, folded cascode, rail-to-rail input | Hand calculation |
| Sizing | Currents, \( g_m/I_D \), lengths and widths | \( g_m/I_D \) curves of the technology |
| Verification | Process, voltage and temperature corners; Monte Carlo | SPICE simulator with the manufacturer's models |
| Layout | Matching, common centroid, guard rings, shielding | Layout editor and parasitic extraction |
02The two-stage op amp
The most widely taught CMOS op amp has a differential pair with a mirror load, a differential stage that provides gain and converts to a single-ended output, followed by a common source with an active load. Each stage contributes a gain on the order of the intrinsic gain of the transistor, and the product easily exceeds 70 dB:
03Miller compensation and the zero
Miller compensation splits the poles: the first goes down and the second goes up to near \( g_{m6}/C_L \). But \( C_c \) also creates a direct path from the input to the output of the second stage, which produces a right-half-plane zero: it adds phase lag like a pole, and takes margin away from the amplifier:
The classic design rules, from Allen and Holberg, call for \( g_{m6} \ge 10\, g_{m1} \) to push the zero away and \( C_c \ge 0.22\, C_L \) so that the second pole lies at more than 2.2 times the GBW: with that the phase margin is around 60°. The slew rate is set by the tail current charging \( C_c \), \( I_5/C_c \), unless the second stage cannot charge the load fast enough: \( (I_6 - I_5)/C_L \).
A two-stage op amp in a 3.3 V process, with \( g_m/I_D = 10\ \mathrm{V^{-1}} \) in all the signal transistors, DC gain 5000 and 0.2 pF of parasitic capacitance at the output of the first stage. It is used as a follower. The curve is the loop gain; the dotted line marks 0 dB.
04Other topologies and blocks
The folded cascode obtains high gain in a single stage: the only high-impedance node is the output, the load itself compensates it and there is no Miller zero. It is the usual choice for capacitive loads, as in switched-capacitor circuits. With a class AB output stage, rail-to-rail swing is obtained, and with two complementary pairs at the input, a rail-to-rail input.
Around the amplifiers, an analog chip needs other blocks: a bandgap reference, which combines the base–emitter voltage, which falls with temperature, with a voltage proportional to absolute temperature to obtain about 1.2 V almost independent of it; a constant-gm bias; internal LDO regulators and data converters. All are designed with the same method: specify, choose the topology, size by hand with \( g_m/I_D \) and verify in the simulator.
05In the lab
Size the two-stage op amp in a SPICE simulator with models of an open technology, such as SKY130, and compare the simulated phase margin with the one calculated by hand.
Repeat the simulation at the process and temperature corners and with Monte Carlo of the offset. Identify which specification is lost first.
Simulate the response to a large step and measure the rising and falling slew rate. Explain the asymmetry.
06Common mistakes
- Forgetting the right-half-plane zero. With small \( g_{m6} \), the zero gets closer and the phase margin calculated with two poles is optimistic.
- Designing for the nominal load. The second pole depends on \( C_L \); with more load the margin falls.
- Shrinking \( C_c \) to gain GBW without looking at the second pole. The GBW goes up and the phase margin goes down.
- Trusting the hand calculation without simulating the corners. Currents and capacitances change with process and temperature.
07Self-assessment
What GBW does an op amp with gm1 = 100 μS and Cc = 2 pF have?
\( 10^{-4}/(2\pi \cdot 2\cdot10^{-12}) \approx 8 \) MHz.
With gm6 = 2 mS and Cc = 2 pF, where is the zero without Rz?
At \( 2\cdot10^{-3}/(2\pi \cdot 2\cdot10^{-12}) \approx 159 \) MHz, in the right half-plane.
What slew rate does a 20 μA tail give with Cc = 2 pF?
10 V/μs.
What value of Rz eliminates the zero?
\( R_z = 1/g_{m6} \).
08Further reading
- Phillip E. Allen and Douglas R. Holberg. CMOS Analog Circuit Design. 3rd ed., Oxford University Press, 2012. The design procedure for the two-stage op amp, step by step.
- Behzad Razavi. Design of Analog CMOS Integrated Circuits. 2nd ed., McGraw-Hill, 2017. Op amps, compensation and the bandgap reference with physical intuition.
- Paul G. A. Jespers and Boris Murmann. Systematic Design of Analog CMOS Circuits Using Pre-Computed Lookup Tables. Cambridge University Press, 2017. Design with \( g_m/I_D \) taken to a systematic method.