Digital signal processing and hardware
A filter with a Blackman window attenuates 75 dB in floating point. With 12-bit coefficients, barely 57: the precision of the hardware decides which filter can be implemented.
01An operation repeated millions of times
Almost all digital signal processing boils down to sums of products. An \( N \)-coefficient FIR filter computes each output sample with \( N \) multiplications and \( N \) additions; so does an FFT, a correlation or an equalizer. The basic operation is multiply-accumulate (MAC):
A general-purpose processor does a MAC in several instructions: two memory reads, a multiplication, an addition and the pointer update. A digital signal processor (DSP) is designed to do it in one cycle.
02The hardware of a DSP
| Resource | What it is for |
|---|---|
| Modified Harvard architecture | Separate buses for instructions and data, and sometimes two for data: the coefficient and the sample are read in the same cycle |
| Hardware multiplier and accumulator | One MAC per cycle, with a wide accumulator |
| Circular addressing | The filter’s delay line without moving data: the pointer wraps back to the start on its own |
| Bit-reversed addressing | The reordering of the FFT with no computation |
| Zero-overhead loops | Repeating a block of instructions without branch instructions |
| DMA | Moving the samples from the converter to memory without using the core |
Today these ideas are also in microcontrollers: the Cortex-M4 and M7 have single-cycle MAC instructions and SIMD operations that process two 16-bit samples at once. For higher bandwidths, FPGAs are used, with hundreds of multipliers in parallel, and GPUs. The general organization of processors was covered in processor architecture.
03Fixed point: Q15, saturation and guard bits
Many DSPs and almost all microcontrollers work in fixed point: the numbers are integers that are interpreted as fractions. In the Q15 format, a 16-bit integer represents values between −1 and 1 − 2⁻¹⁵:
The coefficients are also rounded. A filter designed in floating point, such as those in filter design, changes its response when quantized: the error in each coefficient is noise that fills the stopband, and it limits the attenuation to about 6 dB per bit.
A 51-coefficient low-pass filter with \( f_c = 0.2\, f_s \), designed with a window. The gray curve is the response with floating-point coefficients; the blue one, with coefficients rounded to the chosen number of bits. The attenuation is measured as the worst value above \( 0.26\, f_s \).
04Real time: sample by sample or in blocks
A real-time system has to finish processing each sample before the next one arrives. There are two ways to organize it:
- Sample by sample: one interrupt for each sample from the converter. Latency is minimal, but the cost of entering and leaving the interrupt is paid on every sample.
- In blocks: the DMA fills one buffer while the core processes the other (ping-pong). A whole block is processed with efficient loops, in exchange for a latency of one or two blocks. It is the usual approach in audio and communications.
The \( N \)-point FFT needs \( (N/2) \log_2 N \) butterflies, each with one complex multiplication: 5120 for 1024 points, against more than a million products for the direct DFT. DSPs accelerate it with bit-reversed addressing and, in some cases, with dedicated accelerators.
05In the laboratory
Implement a 51-coefficient Q15 FIR on a Cortex-M4 with the CMSIS-DSP library, processing blocks with DMA from the converter, and measure the computation time with an output pin.
Process a sine wave near full scale with wrap-around addition and with saturation, and listen to or plot the difference.
Measure the response of the implemented filter with a generator and an analyzer, and compare it with the floating-point one.
06Common mistakes
- Designing the filter in floating point and quantizing without checking. The attenuation can drop by tens of dB.
- Accumulating in 16 bits. The products are summed in a wide accumulator and rounded only once at the end.
- Letting the overflow wrap around. You have to saturate, or scale the input so that it does not occur.
- Forgetting the latency of block processing. In a control loop it can make the system unstable.
07Self-assessment
How many MACs per second does a 128-coefficient FIR at 96 kHz in stereo need?
\( 128 \cdot 96\,000 \cdot 2 \approx 24.6 \) million.
What value does the integer 16384 represent in Q15?
0.5.
How many butterflies does a 4096-point FFT have?
\( 2048 \cdot 12 = 24\,576 \).
Why a 40-bit accumulator in a 16-bit DSP?
The products are 32 bits; the 8 guard bits make it possible to add up to 256 full-scale products without overflow.
08Further reading
- Steven W. Smith. The Scientist and Engineer's Guide to Digital Signal Processing. California Technical Publishing, 1997. A practical text, with chapters devoted to DSP architecture.
- Richard G. Lyons. Understanding Digital Signal Processing. 3rd ed., Prentice Hall, 2010. Fixed-point arithmetic and implementation tricks.
- Donald S. Reay. Digital Signal Processing Using the ARM Cortex-M4. Wiley, 2015. Real-time filters and FFT on a microcontroller, with DMA and CMSIS.