Digital Electronics I · 96 h · Topic 2 of 3

Sequential logic

When a digital circuit remembers. Flip-flops store a bit, counters keep count and registers move data. Without this part there would be no memories, digital clocks or microcontrollers.

Digital logic Flip-flops Counters Registers Clock

01Why memory is needed

A combinational circuit always responds the same way to the same input. That is enough to decide, but not to count, nor to sequence, nor to remember that a button was pressed a while ago.

Think of the classroom bell pushbutton: it rings while you hold it down and stops when you release it. That is combinational. Now think of a light switch: you touch it once and the light stays on. That is sequential: the circuit stored a state.

The definition

A circuit is sequential when its output depends on the current inputs and on the internal state, which is a consequence of its past history. It is achieved with just one thing: feedback, that is, taking an output back to an input.

The RS latch: the first circuit with memory

Two cross-coupled NORs are enough. The output of each feeds the other, and that loop is able to hold itself.

Figure 1. RS latch with NOR gates, animated. R = Reset (set to 0), S = Set (set to 1). The essential thing is visible: when the input is released, the output stays where it was. That is memory.

S	R	Next Q	What happens
0	0	Previous Q	Memory. The latch keeps what it had.
0	1	0	Reset. Cleared: Q goes to 0.
1	0	1	Set. Written: Q goes to 1.
1	1	—	Forbidden. Q and Q̅ are both 0: coherence is broken and on release an unpredictable state remains.

The forbidden state

S = R = 1 does not destroy the circuit, but it does destroy the logic: Q stops being the complement of Q̅ and, when both inputs go back to 0, the latch falls to 0 or to 1 depending on which gate reacts first. It is a race condition. All the flip-flops seen later are designed precisely so that this situation cannot occur.

Try it yourself: the latch at work

The simulator reproduces the circuit in Figure 1. Try this sequence: turn S on and off, then turn R on and off. Notice that Q changes when an input is activated and not when it is released. Finally, turn both on and use «Release both at once» to see the race condition.

02The clock and edge triggering

The RS latch reacts the moment an input changes. In a system with many blocks that is a disaster: each one changes whenever it wants and false intermediate results appear. The solution is for all of them to act at the same time, paced by a common signal: the clock (CLK).

Figure 2. Clock signal. The frequency is f = 1/T: if T = 1 ms, f = 1 kHz. Modern flip-flops act on an edge, not during the whole high level.

Level triggering — the flip-flop is transparent for as long as the clock is high. It is called a latch. Problem: if the input changes during that interval, so does the output.
Edge triggering — the flip-flop looks at the input only at the instant of the edge (rising ↑ or falling ↓). Everything that happens between edges is ignored. This is what is used in practice.

In schematic symbols, edge triggering is marked with a small triangle at the clock input. If there is also a small circle before the triangle, triggering is on the falling edge.

03The four flip-flops

D flip-flop (Data / Delay)

It is the most widely used and the simplest to understand: on the clock edge, Q takes the value of D. Between edges, nothing happens. A D flip-flop is literally “a cell that stores one bit.”

Q_{n + 1} = D

Characteristic equation of the D flip-flop. Typical IC: 74LS74 (two D flip-flops) or CD4013.

JK flip-flop

It solves the RS problem: the combination J = K = 1, instead of being forbidden, makes the output change state (it toggles). It is the most versatile flip-flop.

J	K	Next Q	Function
0	0	Q_n	Holds
0	1	0	Reset
1	0	1	Set
1	1	Q̅_n	Toggles on every edge

Q_{n + 1} = J \cdot \overline{Q_{n}} + \overline{K} \cdot Q_{n}

Characteristic equation of the JK. Typical IC: 74LS76 or CD4027.

T flip-flop (Toggle)

It is a JK with both inputs tied together. If T = 1 it toggles on every edge; if T = 0 it holds. It is used to divide the frequency by two, which is the basis of all counters.

Clocked RS flip-flop

It is the RS latch with a gate that enables it only on the clock edge. It keeps the forbidden state S = R = 1, so in practice it has been replaced by the JK and the D.

Type	Inputs	What it does on the edge	Typical use	IC
D	D	Q = D	Registers, memory, synchronizing signals	74LS74 / CD4013
JK	J, K	Set / Reset / hold / toggle	Counters, state machines	74LS76 / CD4027
T	T	Toggles if T = 1	Frequency divider	JK with J=K
RS	S, R	Set / Reset (1,1 forbidden)	Debouncing, interlocks	With 74LS00

Asynchronous inputs: PRESET and CLEAR

Almost all commercial flip-flops come with two more inputs, usually active low (drawn with a small circle and written with an overbar): PR (preset, forces Q = 1) and CLR (clear, forces Q = 0). They are asynchronous: they act immediately, without waiting for the clock.

Lab trap

If a flip-flop “does nothing,” the first thing to check is whether PR and CLR are floating. Because they are active low, they must be connected to +V_CC to stay inactive. Left floating, the circuit gets stuck in one state.

04Counters

A counter is a chain of flip-flops that advances one step on every clock pulse. With $n$ flip-flops it counts through $2^{n}$ states: 4 flip-flops → 16 states (0 to 15).

Asynchronous (ripple) counter

The clock enters only the first flip-flop; the output of each one is the clock of the next. Since each T flip-flop divides by two, the chain divides by 2, 4, 8, 16… and the whole thing counts in binary.

Figure 3. 4-bit asynchronous counter, animated: counts from 0 to 15 with its timing diagram. Simple to build, but the delay accumulates: with 4 stages of 20 ns, the count takes 80 ns to settle.

That accumulated delay produces spurious states: when going from 0111 to 1000, for a few nanoseconds the counter shows 0110, 0100, 0000 and only then 1000. If another circuit is watching that output, it may read a value that never really existed. That is why the asynchronous counter is not used at high frequencies or for decoding states.

Synchronous counter

All the flip-flops receive the same clock at once. What is computed with gates is when each one must toggle: the weight-2 bit toggles when the weight-1 bit is 1; the weight-4 bit toggles when the two previous ones are 1, and so on.

T_{0} = 1

T_{1} = Q_{0}

T_{2} = Q_{0} \cdot Q_{1}

T_{3} = Q_{0} \cdot Q_{1} \cdot Q_{2}

Enable equations of a 4-bit synchronous up counter.

All outputs change simultaneously, there are no spurious states and the maximum speed is set by a single delay, not by their sum. This is what is inside the 74LS163 or the CD4520.

Counters with a modulus other than 2ⁿ

To count from 0 to 9 (decade counter, modulus 10) a 4-bit counter is used and state 1010 (=10) is detected with an AND gate that drives the asynchronous CLEAR, forcing a return to 0000. It is the standard trick and also the source of a problem: for a few nanoseconds the counter “passes through” 10 before clearing, which produces a spurious flash on the display.

Counter	Modulus	Type	Remarks
74LS90	10	Asynchronous	Classic decade counter, widely used in frequency counters.
74LS93	16	Asynchronous	4-bit binary.
74LS163	16	Synchronous	With parallel load and synchronous clear.
74LS192	10	Synchronous	Counts up and down (up/down).
CD4017	10	Johnson	10 decoded outputs: one active at a time. Ideal for light sequences.
CD4040	4096	Asynchronous	12 stages. Frequency divider.

05Shift registers

A register is a row of D flip-flops with the same clock. If the output of each one is connected to the input of the next, on every edge the contents shift one place. That is a shift register.

Serial → parallel

One bit enters at a time and, after $n$ pulses, all $n$ bits are available at once. This is how data is received over a single wire. IC: 74LS164 or CD4015.

Parallel → serial

$n$ bits are loaded at once and leave one at a time over a single wire. This is how data is transmitted. IC: 74LS165.

These two blocks are the basis of all serial communication: the USART of a microcontroller, the SPI bus of a sensor, a USB cable. Many wires are traded for a single one at the cost of time.

Immediate application: the LED matrix

The 74HC595 IC is a serial-in, parallel-out shift register with latched outputs. With three wires from a microcontroller you drive 8 outputs, and by chaining several, 32 or 64. It is the standard solution for LED signs and is a direct topic of Years 6 and 7.

06A real problem: pushbutton bounce

When a mechanical pushbutton is pressed, the contacts do not close cleanly: they bounce for 5 to 20 ms, generating dozens of pulses. A combinational circuit does not notice, but a counter counts all those bounces and instead of adding 1 it adds 12.

Figure 4. Contact bounce and its correction. It is the most common defect in the projects of this course.

Three solutions, from the least to the most polished:

RC filter + Schmitt trigger — a 10 kΩ resistor and a 100 nF capacitor ahead of a 74LS14 (inverter with hysteresis). Cheap and very effective.
RS latch with NANDs and a changeover pushbutton: as soon as the contact touches the first terminal, the latch changes state and no longer cares what happens afterward.
In software, on a microcontroller: read, wait 20 ms and read again. This is covered in Year 6.

07In the lab

Lab 1 · RS latch with NANDs

With a 74LS00, cross-couple two NANDs. The inputs (active low, S̅ and R̅) are taken to ground with pushbuttons and to V_CC with 1 kΩ resistors. Two LEDs on Q and Q̅. Verify that the outputs are always opposite and that the memory holds when the pushbuttons are released.

Lab 2 · Frequency divider

With a 74LS76 (two JKs) connected with J = K = 1 in cascade, and a 555 in astable mode at 1 Hz as the clock. One LED on each output. You can see it directly: the first LED blinks at 0.5 Hz, the second at 0.25 Hz. Measure with the oscilloscope and verify the frequency relationship.

Lab 3 · Decade counter with display

555 in astable mode → 74LS90 (0-to-9 counter) → 74LS47 → common-anode 7-segment display with seven 330 Ω resistors. It is the classic capstone project of the unit, because it uses the combinational (the decoder) and the sequential (the counter) together. Add a debounced pushbutton to count by hand.

⏱️ LM555 simulator Astable and monostable modes with an animated schematic, live frequency calculation and reverse design with E12 values. Useful for generating the clock for these labs. › 🔢 Interactive Digital Logic course Its fourth tab develops sequential logic: an animated D flip-flop and a step-by-step serial-to-parallel shift register. ›

08Common mistakes

Symptom	Usual cause
The flip-flop does not respond to the clock	PRESET or CLEAR floating or low. They must go to V_CC to stay inactive.
The counter skips numbers	Bounce of the pushbutton used as the clock. Debouncing is missing.
The counter counts backwards	Q̅ was taken instead of Q for chaining, or the flip-flop triggers on the opposite edge from the one expected.
The display shows a strange flash when recycling	Spurious state of the asynchronous counter with CLEAR through an AND. Fixed with a synchronous counter or with an output latch.
Everything works but erratically at high frequency	Accumulated delay of the ripple counter, or missing decoupling capacitors.
The count starts at a random number	The flip-flops power up in an undefined state. You must apply a CLEAR at power-up (RC on the reset input).

09Self-assessment

What is the essential difference between a combinational and a sequential circuit?

The sequential one has memory: its output depends on the current inputs and on the internal state. Physically, this is achieved with feedback of an output to an input.

Why is S = R = 1 said to be a forbidden state in the RS latch?

Because Q and Q̅ stop being complementary (both are 0 with NOR) and, above all, because when the inputs return to 0 the latch ends up at 0 or at 1 depending on which gate responds first: the result is unpredictable.

A T flip-flop with T = 1 receives an 8 kHz signal. What frequency comes out at Q?

4 kHz. It toggles on every active edge, so it takes two input pulses to complete one output cycle: it divides by two.

How many flip-flops are needed to count up to 100?

You have to cover 101 states (0 to 100). With 6 flip-flops you reach 64, which is not enough; with 7 you reach 128, which is enough. The rule is the smallest n such that 2ⁿ ≥ number of states.

A concrete advantage of the synchronous counter over the asynchronous one.

All the outputs change at once, so there are no spurious states and the maximum frequency does not drop when stages are added (the delay does not accumulate). In return, it needs more gates.

How do you turn a JK flip-flop into a T? And into a D?

Into a T: tie J to K (that tie is the T input). Into a D: connect J = D and K = D̅, that is, put an inverter between the two inputs.

What is a serial-to-parallel shift register for?

To receive data that arrives bit by bit over a single wire and present it complete, in parallel, once it has finished coming in. It is what the receiving side of any serial communication does (USART, SPI).

A 4-bit counter has to recycle at 12. Which state must be detected and what is done with it?

State 1100 (=12) is detected with an AND on Q3 and Q2, and that output drives the asynchronous CLEAR to return to 0000. This way the counter runs through 0 to 11, which is 12 states.

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