Digital Electronics II · 96 h · Topic 1 of 4

Programmable counters

A counter is a frequency divider and a state register at the same time. What makes it programmable is being able to decide, by hardware —or by software, later on— what number it starts at, where it stops and which way it counts. All digital timing comes from here.

Sequential logic Counter ICs Frequency division Cascading

01Where we come from: counting is dividing

In sequential logic we built counters from discrete flip-flops. Now we use counter integrated circuits, which have everything worked out inside and add the pins that let you program them. But the underlying idea has not changed, and it is worth keeping in mind because it explains every application:

The idea to see in the timing diagram

Each stage of a binary counter divides the frequency by two. Q0 changes once for every clock pulse, Q1 once every two, Q2 once every four. A counter of n stages is therefore, at the same time, a modulo-2ⁿ counter and a divide-by-2ⁿ divider. The same pin can be used to read a number or to output a lower frequency.

Figure 1. A 4-bit binary counter, animated. The cursor steps through the 16 states: the waveform of each output on the left, the lamps and the decimal number on the right. You can see that Q0 is f/2, Q1 f/4, Q2 f/8 and Q3 f/16.

Stages	Counts up to	Modulus	Frequency division
4 (a binary decade)	15	16	f/16 at the last output
8	255	256	f/256
12	4095	4096	f/4096
14 (CD4020)	16383	16384	f/16384
24 (CD4521)	16777215	2²⁴	32768 Hz → 1 Hz with 15 stages

That last row is the quartz wristwatch clock: a 32,768 Hz crystal —which is 2¹⁵— divided fifteen times gives exactly one pulse per second. Watch crystals have that value precisely because it comes out round in a chain of flip-flops.

02Asynchronous and synchronous: the difference that matters

Both count the same way. The difference lies in when each stage changes, and it is paid for in speed and in false pulses.

Asynchronous (ripple)

The clock enters only the first stage; each flip-flop triggers the next. The changes propagate down the chain.

Less internal circuitry, cheaper: the CD4040 fits 12 stages in a DIP16.
Total delay = n × t_PLH. With 12 stages of 10 ns that is 120 ns of skew.
During that skew false intermediate states appear: going from 0111 to 1000 the counter shows 0110, 0100, 0000 and only then 1000.
It works as a frequency divider, not for decoding states.

Synchronous

The clock reaches all stages at once; a network of gates decides which ones change on that edge.

All outputs change together: there are no false states.
The maximum frequency does not depend on the number of stages.
It is the only kind you can decode safely (for example, to light a display or trigger an actuator).
Almost all programmable counters —74190/191/192/193, 4029, 4510, 4516— are synchronous.

The decoding glitch

If you decode state 8 (1000) of an asynchronous counter with an AND gate, that gate also becomes active for a few nanoseconds during the 7 → 8 transition, while the stages settle. A fast oscilloscope sees it as a spike. A flip-flop connected to that output takes it for a real pulse and the circuit fails once in a while, with no apparent pattern. It is one of the hardest faults to find on the bench. The fix: a synchronous counter, or qualify the decoding with the clock.

03The catalog used in the shop

You do not need to memorize it, but you should know which family to look in. The complete datasheets for the 40XX series are collected in the site’s digital logic publication.

IC	Type	Modulus	Why you choose it
7490	Asynchronous	2 + 5 = 10	The classic TTL decade counter. It has two separate sections: ÷2 and ÷5. Reset to 0 and reset to 9.
7493	Asynchronous	2 + 8 = 16	Same as the previous one but binary. It is the one used to build odd moduli with reset.
74192 / 74193	Synchronous	10 / 16	Counts up and down through two separate clock inputs. With parallel load. The workhorse of the TTL programmable counter.
74190 / 74191	Synchronous	10 / 16	Same, but with a single clock and a U/D̄ pin that selects the direction.
74163	Synchronous	16	Synchronous load and clear: it does not generate false pulses. The favorite for load-based moduli.
CD4017	Johnson	10	Ten decoded outputs: one lights at a time. Sequencers and lights.
CD4020 / 4040 / 4060	Asynchronous	2¹⁴ / 2¹² / 2¹⁴	Long dividers. The 4060 also has the crystal oscillator built in.
CD4029	Synchronous	10 or 16	Programmable in every respect: direction, binary or BCD, with parallel load. Widely used in CMOS.
CD4510 / 4516	Synchronous	10 / 16	The CMOS equivalents of the 74192/193.
CD4553 / 4026 / 4033	Synchronous	10	Counter + seven-segment decoder on the same chip. Frequency counters and tachometers.

The pins you should recognize on any counter

CLK — clock. Check whether it is active on the rising edge (↑) or the falling edge (↓); the symbol on the datasheet is a small triangle, with a circle if it is falling-edge.
CLR / MR / RESET — takes the count to zero. It can be asynchronous (acts as soon as it arrives) or synchronous (waits for the clock edge).
LOAD / PE — loads the number present on the parallel inputs into the outputs.
P0…P3 / J1…J4 — parallel inputs: the number that gets loaded.
U/D̄ — count direction.
CE / ENT / ENP — enable. With the enable inactive the counter is frozen but not cleared.
TC / RCO / CARRY — “terminal count”: signals that the end of the count was reached. It is the pin used to build the cascade.

04Programming the modulus: the two ways

A 74193 counts to 16 and a 4510 to 10. What if you need to count to 6, as in the seconds of a clock, or to 12? You shorten its count. There are two techniques and they are not equivalent.

a) By reset: detect state N and clear

A gate decodes the first state that you do not want and sends it to the reset. The counter goes through that state for an instant and returns to zero.

Figure 2. Modulo 6 by asynchronous reset, animated. The count reaches 6 (110), the AND of Q1·Q2 triggers the clear and the state lasts barely the propagation delay: the phantom state, marked in red. That is why the modulus is 6 even though 6 is decoded.

The phantom state

That lightning-fast pass through state 6 has three practical consequences:

If a display is connected to the outputs, the extra digit can flicker. At high brightness it becomes noticeable.
If another circuit reads those outputs, it may take the 6 as a valid value.
The reset pulse is very narrow (tens of nanoseconds). In slow CMOS it sometimes does not even clear all the flip-flops and the counter hangs in a strange state. The fix is a flip-flop that stretches the pulse, or using the other technique.

b) By synchronous load: much cleaner

With a counter that has synchronous load and clear (74163, or the 74193 using its parallel load), the correction happens on the clock edge, together with all the other changes. There is no phantom state and no narrow pulse.

Two forms of the same count

To count N states with a 4-bit counter there are two symmetric paths:

Counting up: load the initial value 16 − N and use the output carry (which appears at 15) to reload it. Example: for N = 6, load 10 and it counts 10, 11, 12, 13, 14, 15 → reload.
Counting down: load N − 1 and reload when it reaches 0. For N = 6, load 5 and it counts 5, 4, 3, 2, 1, 0 → reload. This is the form microcontroller timers use, and that is why it is worth getting used to it.

Example · The seconds of a digital clock

The seconds run from 00 to 59: you need a full decade for the units and a modulo 6 for the tens.

Units: a 4510 in BCD mode, modulus 10, with nothing added. Its carry comes out once every 10 seconds.
Tens: another 4510 whose 6 is decoded with an AND between Q1 and Q2 (110 = 6) feeding the reset. It counts 0…5 and starts over.
The carry of the tens, once every 60 s, feeds the minutes counter.

The total modulus of the pair is 10 × 6 = 60. The input has to be exactly 1 Hz: that is why a quartz clock divides 32,768 by 2¹⁵, or why a simple version starts from the 50 Hz mains, dividing by 50.

05Expansion: cascading counters

A single IC only counts up to 10 or 16. Everything else is built by chaining, and how you chain them is what separates a cascade that works at 20 MHz from one that hangs at 2 MHz.

Figure 3. A cascade of three decades, animated. Each carry is ten times slower than the previous one. It is the skeleton of a frequency counter, of a tachometer and of the counter in any clock.

Clock cascade (ripple)

The carry of one stage is connected to the clock of the next. This is what is done with asynchronous counters and with the 74192/193.

Simple, but the delays add up stage by stage and the outputs do not all change together.

Enable cascade

The clock enters all stages at once and the carry is connected to the enable of the next: the high stage counts only on the edge where the low one is in its last state.

The whole assembly remains synchronous, no matter how many stages it has. It is the right way when the count has to be decoded.

Moduli that are not powers of ten

The total modulus of a cascade is the product of the moduli. Two decades and a modulo 6 give 600; a modulo 6 and a modulo 10, the 60 seconds. If you need a prime modulus or any odd number —for example dividing 50 Hz by 50 to get 1 Hz— it is better to build a single long binary counter and decode the final value, instead of chaining small moduli.

06The 4017: counting without decoding

It is a case apart and deserves its own section because it solves an entire problem by itself. Inside there is no binary counter but a ring shift register (Johnson) with the decoding already done: instead of four binary outputs it has ten outputs, and on each pulse only one lights up.

Figure 4. CD4017, animated. The active output “walks” from Q0 to Q9 on each clock edge. Connecting any output to RESET gives a sequencer with fewer steps: with Q6 to reset, the cycle becomes six steps long.

What you can build with it in two minutes

Sequential lights of the Knight Rider kind (with the 4017 + a 555 as the clock).
Step sequencer for a motor.
A divider by any number from 2 to 10, by taking output N to the reset.
Timing distributor for multiplexing displays.

Its particular pins

CP0 advances on the rising edge; CP1 (inhibit) is used to stop it or to use the falling edge.
MR (reset) returns to Q0. Active high.
Q5-9 is a carry output that stays high for half of the cycle: it is used to chain 4017s with no extra logic.

The clock that makes it advance almost always comes from a 555 astable: there you can choose the speed of the sequencer with a single R-C pair.

07Typical applications

Frequency counter

A cascade of decades whose input is opened by a gate for exactly 1 s. What is left in the counter is the hertz. It is the circuit studied in AC measurements and that is taken up in full in digital instruments.

Digital clock

1 Hz timebase → modulo 60 (seconds) → modulo 60 (minutes) → modulo 12 or 24 (hours). Each block is the same pair of counters with a different reset.

Programmable frequency divider

A down counter that is reloaded with a number N every time it reaches zero delivers f/N. By changing N —with switches, a keypad or from a microcontroller— you change the division. It is the heart of a PLL synthesizer, which is used to choose the frequency of a transmitter.

Ramp digital-to-analog conversion

A counter that drives an R-2R network generates a staircase ramp. Compared against a signal, it gives a ramp A/D converter, covered in A/D and D/A converters.

Worked example · A motor tachometer

An optical sensor delivers one pulse per revolution of a shaft turning at 1500 RPM. You want to show the revolutions per minute on three digits.

1500 RPM = 1500/60 = 25 pulses per second.
If you count for 1 s you read 25: but you have to show RPM, not pulses per second. So you count for 60 s, or you multiply by 60 by choosing a 1 s window and counting pulses from a 60-slot disc.
Practical solution: a 6-slot disc and a 1 s window. You count 1500 × 6/60 = 150 pulses, and the display directly shows the hundreds and tens of RPM with a fixed decimal position (150 → 1500 RPM, with the last zero printed on the front panel).
Three decades in cascade (modulus 1000) and a window gate are needed. With the result at 150 out of 999, the range reaches up to 9990 RPM.

08In the lab

Lab 1 · Division by two, seen on the oscilloscope

Build a CD4040 with a 10 kHz clock from the function generator. With the two-channel oscilloscope, leave channel 1 on the clock and move channel 2 through outputs Q1 to Q6, measuring the frequency at each one. Record the table: 5 kHz, 2.5 kHz, 1.25 kHz, 625 Hz, 312.5 Hz, 156.25 Hz. It is the direct proof that counting and dividing are the same thing.

Lab 2 · Modulus on demand

With a 74193 (or 4516) and a four-input NAND gate, build moduli 5, 7, 9 and 12 in turn by reset. Check each one with LEDs on the four outputs and a very slow clock (1 Hz from a 555). Then repeat modulus 12 by parallel load and compare on the oscilloscope the Q3 output in the two cases: in the reset version you can see the spike of the phantom state.

Lab 3 · Seconds clock

1 Hz timebase + 4510 decade + modulo 6, with two seven-segment displays through 4511s. Verify that the count goes from 00 to 59 and back to 00 without skipping 59 or showing a flickering 60. If the 60 appears, the reset is not taken from the right outputs.

Lab 4 · Sequencer with a 4017

555 astable at 2 Hz → 4017 → ten LEDs. Then take Q6 to the reset and check that the cycle becomes six steps. Finally, use the Q5-9 output to chain a second 4017 and build a twenty-step sequencer.

Floating CMOS inputs

In CMOS no input may be left unconnected, not even the unused ones. A floating input takes any value, oscillates and makes the IC draw current. All unused reset, load and enable inputs go to ground or to V_DD as appropriate. It is the number one cause of CMOS counters that “count anything”.

09Errores frecuentes

Symptom	Usual cause
The counter skips numbers or counts by twos	Bounce of the pushbutton used as the clock. A debouncer is needed (R-C + Schmitt, or a 555 monostable).
The count hangs at an odd number	Reset pulse too narrow, or unconnected CMOS inputs.
The display shows an extra digit, flickering	Phantom state of the asynchronous-reset modulus. Switch to synchronous load or blank the display during the reset.
In the cascade, the high stage advances twice	The carry was taken by level instead of by edge, or it was connected to a clock of the opposite edge from the one required.
It works slowly and fails as the frequency goes up	Ripple-type cascade: the accumulated delays exceed the clock period. Switch to an enable cascade.
The decoding fires on its own	Decoding glitch on an asynchronous counter. Qualify with the clock or use a synchronous one.
It counts fine with LEDs but fails when driving a relay	The coil noise comes back through the supply. Decouple with 100 nF at each IC and a flyback diode on the relay.
The 4017 lights two outputs at once	Clock with dirty or slow edges. Pass the signal through a Schmitt trigger (40106).

10Self-assessment

How many flip-flops are needed for a modulo-12 counter, and what is its real capacity?

Four, because with three you only reach 8. The natural capacity of four stages is 16, so the count has to be shortened: decode 12 (1100) to the reset, or load 4 and count up to the overflow.

Why is a watch crystal 32,768 Hz?

Because 32,768 = 2¹⁵. Fifteen stages of binary division —which is what is inside any counter— deliver exactly 1 Hz with no correction.

What is the phantom state and how is it eliminated?

It is the very brief pass through the state that is decoded to reset: the counter reaches that value and only then is cleared, so it exists for the propagation delay. It is eliminated by programming the modulus with synchronous load, or with a synchronous-clear counter such as the 74163.

With three decades in cascade and a 1 MHz clock, what frequency comes out of the last one?

1 MHz / (10 × 10 × 10) = 1000 Hz. Each decade divides by ten.

Why can an asynchronous counter not be decoded safely?

Because its stages do not change at the same time: during propagation, intermediate combinations appear that do not correspond to any state of the count. A decoding gate sees them and generates false pulses a few nanoseconds long.

You want to divide a signal by 7. How is it done with a 4-bit counter?

Two ways. Up: decode 7 (0111) to the reset, so that the counter runs through 0…6 and starts over: seven states. Down and clean: load 6 and reload on reaching 0, or load 16 − 7 = 9 and reload with the carry. The second has no phantom state.

What advantage does the 4017 have over a 4510 with a decoder?

It already comes with the ten outputs decoded and guarantees that only one is active at a time, with no glitches. It saves the decoder and the risk of two outputs overlapping during the transition.

In an enable cascade, where does the clock of the second stage go?

To the same clock as the first. What goes from the carry of the first to the second is the count enable, not the clock. That way the whole assembly changes on the same edge and remains synchronous.

A 4-bit counter starts at 0110 as soon as the circuit is powered on, without having counted anything. What is going on?

The flip-flops take a random state at power-up. A power-on reset is missing: an R-C that applies a clear pulse during the first milliseconds.

Why does a microcontroller timer count down?

Because detecting zero is cheaper than comparing against an arbitrary number: a NOR of all the bits is enough. By counting down from N − 1 any modulus is programmed with the same detection logic.

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