Hardware description languages

01Describing hardware, not programming it

A hardware description language (HDL) looks like a programming language and is not one. A C program is a list of instructions that a processor executes one at a time, in order. A description in VHDL or Verilog is the description of a circuit: each statement is a piece of hardware that exists and works at the same time as all the others. There is no “now this line runs”; there are gates and flip-flops that all react at once to their inputs.

That change of mindset is the main difficulty of this unit, and almost all the mistakes of someone learning HDL come from writing as if it were C: expecting things to happen in order, using variables as in a program, or writing a loop expecting it to repeat in time when in fact it will be unrolled into copied hardware.

02VHDL and Verilog

Two languages have dominated digital design since the 1980s, and every FPGA tool accepts both:

The same four-bit counter with synchronous reset, in both:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
  port (clk, rst : in  std_logic;
        q        : out unsigned(3 downto 0));
end;

architecture rtl of counter is
  signal c : unsigned(3 downto 0);
begin
  process (clk) begin
    if rising_edge(clk) then
      if rst = '1' then c <= (others => '0');
      else             c <= c + 1;
      end if;
    end if;
  end process;
  q <= c;
end;VHDL

module counter (
  input            clk, rst,
  output reg [3:0] q
);
  always @(posedge clk)
    if (rst) q <= 4'd0;
    else     q <= q + 4'd1;
endmoduleVerilog

Both describe exactly the same circuit: four D flip-flops, a four-bit adder that adds one, and a multiplexer that chooses between the sum and zero depending on the reset. Neither of them “counts” in the sense of a program: they describe the connections that, edge by edge, make the hardware count.

03Blocking and nonblocking

In Verilog there are two ways to assign inside a clocked block, and confusing them produces circuits different from the ones intended:

04Simulation and synthesis

One HDL file has two destinations. The simulator runs it to see how it behaves over time; the synthesizer translates it into real gates and flip-flops. Not everything that simulates can be synthesized:

That is why every design is verified with a testbench (test bench): a module that is not synthesized, that generates the stimuli, observes the outputs and compares them with what is expected. In industry, writing the verification takes more work than writing the design.

05Differences from a procedural language

06Where it shows up in electronics

07In the lab

08Common mistakes

• Thinking of statements as steps in time. They are parts of a circuit that work at the same time.
• Using blocking assignment in a clocked block. It collapses registers and breaks shifts and swaps.
• Leaving an if without else in combinational logic. It generates a latch.
• Expecting #10 to produce a delay in the FPGA. The synthesizer ignores it.
• Not writing a testbench. What was not simulated fails on the board.

09Self-assessment

10Further reading

• Pong P. Chu. FPGA Prototyping by VHDL Examples. 2nd ed., Wiley, 2017. VHDL learned by building real circuits on a board, with synthesis always in view.
• Samir Palnitkar. Verilog HDL: A Guide to Digital Design and Synthesis. 2nd ed., Prentice Hall, 2003. The classic Verilog text, with its chapter on blocking and nonblocking assignments.
• Clifford E. Cummings. Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!. SNUG San José, 2000. The paper that set the style rules the whole industry uses today.